Lines Matching refs:bs
154 static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
157 return readb(bs->regs + bs->reg_offsets[offset]);
160 static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
163 writeb(value, bs->regs + bs->reg_offsets[offset]);
166 static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
170 iowrite16be(value, bs->regs + bs->reg_offsets[offset]);
172 writew(value, bs->regs + bs->reg_offsets[offset]);
189 struct bcm63xx_spi *bs = spi_controller_get_devdata(spi->controller);
205 reg = bcm_spi_readb(bs, SPI_CLK_CFG);
209 bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
220 struct bcm63xx_spi *bs = spi_controller_get_devdata(spi->controller);
229 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
241 memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
261 reinit_completion(&bs->done);
267 msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
269 msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
271 msg_ctl |= (SPI_HD_W << bs->msg_type_shift);
273 switch (bs->msg_ctl_width) {
275 bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
278 bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
286 bcm_spi_writew(bs, cmd, SPI_CMD);
289 bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
291 timeout = wait_for_completion_timeout(&bs->done, HZ);
303 memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
318 struct bcm63xx_spi *bs = spi_controller_get_devdata(host);
346 total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
347 (!can_use_prepend && total_len > bs->fifo_size)) {
349 total_len, bs->fifo_size);
399 struct bcm63xx_spi *bs = spi_controller_get_devdata(host);
403 intr = bcm_spi_readb(bs, SPI_INT_STATUS);
404 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
405 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
409 complete(&bs->done);
416 struct bcm63xx_spi *bs = spi_controller_get_devdata(spi->controller);
418 return bs->fifo_size;
484 struct bcm63xx_spi *bs;
528 host = spi_alloc_host(dev, sizeof(*bs));
534 bs = spi_controller_get_devdata(host);
535 init_completion(&bs->done);
538 bs->pdev = pdev;
540 bs->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
541 if (IS_ERR(bs->regs)) {
542 ret = PTR_ERR(bs->regs);
546 bs->irq = irq;
547 bs->clk = clk;
548 bs->reg_offsets = bcm63xx_spireg;
549 bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE];
567 bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT];
568 bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH];
569 bs->tx_io = (u8 *)(bs->regs + bs->reg_offsets[SPI_MSG_DATA]);
570 bs->rx_io = (const u8 *)(bs->regs + bs->reg_offsets[SPI_RX_DATA]);
573 ret = clk_prepare_enable(bs->clk);
583 bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
595 r, irq, bs->fifo_size);
611 struct bcm63xx_spi *bs = spi_controller_get_devdata(host);
614 bcm_spi_writeb(bs, 0, SPI_INT_MASK);
617 clk_disable_unprepare(bs->clk);
623 struct bcm63xx_spi *bs = spi_controller_get_devdata(host);
627 clk_disable_unprepare(bs->clk);
635 struct bcm63xx_spi *bs = spi_controller_get_devdata(host);
638 ret = clk_prepare_enable(bs->clk);