Lines Matching defs:qspi
25 #include "spi-bcm-qspi.h"
255 static inline bool has_bspi(struct bcm_qspi *qspi)
257 return qspi->bspi_mode;
261 static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi)
263 if (!has_bspi(qspi) &&
264 ((qspi->mspi_maj_rev >= 1) &&
265 (qspi->mspi_min_rev >= 5)))
272 static inline bool bcm_qspi_has_sysclk_108(struct bcm_qspi *qspi)
274 if (!has_bspi(qspi) && (qspi->mspi_spcr3_sysclk ||
275 ((qspi->mspi_maj_rev >= 1) &&
276 (qspi->mspi_min_rev >= 6))))
282 static inline int bcm_qspi_spbr_min(struct bcm_qspi *qspi)
284 if (bcm_qspi_has_fastbr(qspi))
285 return (bcm_qspi_has_sysclk_108(qspi) ? 4 : 1);
302 /* Read qspi controller register*/
303 static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type,
306 return bcm_qspi_readl(qspi->big_endian, qspi->base[type] + offset);
309 /* Write qspi controller register*/
310 static inline void bcm_qspi_write(struct bcm_qspi *qspi, enum base_type type,
313 bcm_qspi_writel(qspi->big_endian, data, qspi->base[type] + offset);
317 static int bcm_qspi_bspi_busy_poll(struct bcm_qspi *qspi)
323 if (!(bcm_qspi_read(qspi, BSPI, BSPI_BUSY_STATUS) & 1))
327 dev_warn(&qspi->pdev->dev, "timeout waiting for !busy_status\n");
331 static inline bool bcm_qspi_bspi_ver_three(struct bcm_qspi *qspi)
333 if (qspi->bspi_maj_rev < 4)
338 static void bcm_qspi_bspi_flush_prefetch_buffers(struct bcm_qspi *qspi)
340 bcm_qspi_bspi_busy_poll(qspi);
342 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 1);
343 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 1);
344 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
345 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
348 static int bcm_qspi_bspi_lr_is_fifo_empty(struct bcm_qspi *qspi)
350 return (bcm_qspi_read(qspi, BSPI, BSPI_RAF_STATUS) &
354 static inline u32 bcm_qspi_bspi_lr_read_fifo(struct bcm_qspi *qspi)
356 u32 data = bcm_qspi_read(qspi, BSPI, BSPI_RAF_READ_DATA);
359 if (bcm_qspi_bspi_ver_three(qspi))
365 static inline void bcm_qspi_bspi_lr_start(struct bcm_qspi *qspi)
367 bcm_qspi_bspi_busy_poll(qspi);
368 bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
372 static inline void bcm_qspi_bspi_lr_clear(struct bcm_qspi *qspi)
374 bcm_qspi_write(qspi, BSPI, BSPI_RAF_CTRL,
376 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
379 static void bcm_qspi_bspi_lr_data_read(struct bcm_qspi *qspi)
381 u32 *buf = (u32 *)qspi->bspi_rf_op->data.buf.in;
384 dev_dbg(&qspi->pdev->dev, "xfer %p rx %p rxlen %d\n", qspi->bspi_rf_op,
385 qspi->bspi_rf_op->data.buf.in, qspi->bspi_rf_op_len);
386 while (!bcm_qspi_bspi_lr_is_fifo_empty(qspi)) {
387 data = bcm_qspi_bspi_lr_read_fifo(qspi);
388 if (likely(qspi->bspi_rf_op_len >= 4) &&
390 buf[qspi->bspi_rf_op_idx++] = data;
391 qspi->bspi_rf_op_len -= 4;
394 u8 *cbuf = (u8 *)&buf[qspi->bspi_rf_op_idx];
397 while (qspi->bspi_rf_op_len) {
400 qspi->bspi_rf_op_len--;
406 static void bcm_qspi_bspi_set_xfer_params(struct bcm_qspi *qspi, u8 cmd_byte,
409 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0);
410 bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_CYCLE, bpc);
411 bcm_qspi_write(qspi, BSPI, BSPI_BITS_PER_PHASE, bpp);
412 bcm_qspi_write(qspi, BSPI, BSPI_CMD_AND_MODE_BYTE, cmd_byte);
413 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, flex_mode);
416 static int bcm_qspi_bspi_set_flex_mode(struct bcm_qspi *qspi,
425 dev_dbg(&qspi->pdev->dev, "set flex mode w %x addrlen %x hp %d\n",
458 bcm_qspi_bspi_set_xfer_params(qspi, command, bpp, bpc, flex_mode);
463 static int bcm_qspi_bspi_set_override(struct bcm_qspi *qspi,
468 u32 data = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
470 dev_dbg(&qspi->pdev->dev, "set override mode w %x addrlen %x hp %d\n",
502 bcm_qspi_write(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL, data);
503 bcm_qspi_bspi_set_xfer_params(qspi, op->cmd.opcode, 0, 0, 0);
508 static int bcm_qspi_bspi_set_mode(struct bcm_qspi *qspi,
516 qspi->xfer_mode.flex_mode = true;
518 if (!bcm_qspi_bspi_ver_three(qspi)) {
521 val = bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
523 if (val & mask || qspi->s3_strap_override_ctrl & mask) {
524 qspi->xfer_mode.flex_mode = false;
525 bcm_qspi_write(qspi, BSPI, BSPI_FLEX_MODE_ENABLE, 0);
526 error = bcm_qspi_bspi_set_override(qspi, op, hp);
530 if (qspi->xfer_mode.flex_mode)
531 error = bcm_qspi_bspi_set_flex_mode(qspi, op, hp);
534 dev_warn(&qspi->pdev->dev,
537 } else if (qspi->xfer_mode.width != width ||
538 qspi->xfer_mode.addrlen != addrlen ||
539 qspi->xfer_mode.hp != hp) {
540 qspi->xfer_mode.width = width;
541 qspi->xfer_mode.addrlen = addrlen;
542 qspi->xfer_mode.hp = hp;
543 dev_dbg(&qspi->pdev->dev,
545 qspi->curr_cs,
546 qspi->xfer_mode.width,
547 qspi->xfer_mode.addrlen,
548 qspi->xfer_mode.hp != -1 ? ", hp mode" : "");
554 static void bcm_qspi_enable_bspi(struct bcm_qspi *qspi)
556 if (!has_bspi(qspi))
559 qspi->bspi_enabled = 1;
560 if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1) == 0)
563 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
565 bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 0);
569 static void bcm_qspi_disable_bspi(struct bcm_qspi *qspi)
571 if (!has_bspi(qspi))
574 qspi->bspi_enabled = 0;
575 if ((bcm_qspi_read(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL) & 1))
578 bcm_qspi_bspi_busy_poll(qspi);
579 bcm_qspi_write(qspi, BSPI, BSPI_MAST_N_BOOT_CTRL, 1);
583 static void bcm_qspi_chip_select(struct bcm_qspi *qspi, int cs)
588 if (cs >= 0 && qspi->base[CHIP_SELECT]) {
589 rd = bcm_qspi_read(qspi, CHIP_SELECT, 0);
593 bcm_qspi_write(qspi, CHIP_SELECT, 0, wr);
597 dev_dbg(&qspi->pdev->dev, "using cs:%d\n", cs);
598 qspi->curr_cs = cs;
611 static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
616 if (!bcmspi_parms_did_change(xp, &qspi->last_parms))
619 if (!qspi->mspi_maj_rev)
636 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
638 if (bcm_qspi_has_fastbr(qspi)) {
647 if (bcm_qspi_has_sysclk_108(qspi)) {
653 qspi->base_clk = MSPI_BASE_FREQ;
657 qspi->base_clk = MSPI_BASE_FREQ * 4;
670 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 1);
681 bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr);
685 qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2);
686 spbr = bcm_qspi_calc_spbr(qspi->base_clk, xp);
687 spbr = clamp_val(spbr, bcm_qspi_spbr_min(qspi), QSPI_SPBR_MAX);
688 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spbr);
690 qspi->last_parms = *xp;
693 static void bcm_qspi_update_parms(struct bcm_qspi *qspi,
703 bcm_qspi_hw_set_parms(qspi, &xp);
731 static bool bcm_qspi_mspi_transfer_is_last(struct bcm_qspi *qspi,
735 spi_transfer_is_last(qspi->host, qt->trans))
741 static int update_qspi_trans_byte_count(struct bcm_qspi *qspi,
766 if (bcm_qspi_mspi_transfer_is_last(qspi, qt))
774 dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n",
779 static inline u8 read_rxram_slot_u8(struct bcm_qspi *qspi, int slot)
784 return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff;
787 static inline u16 read_rxram_slot_u16(struct bcm_qspi *qspi, int slot)
793 return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) |
794 ((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8);
797 static inline u32 read_rxram_slot_u32(struct bcm_qspi *qspi, int slot)
803 val = bcm_qspi_read(qspi, MSPI, offset);
809 static inline u64 read_rxram_slot_u64(struct bcm_qspi *qspi, int slot)
816 msb = bcm_qspi_read(qspi, MSPI, msb_offset);
818 lsb = bcm_qspi_read(qspi, MSPI, lsb_offset);
824 static void read_from_hw(struct bcm_qspi *qspi, int slots)
829 bcm_qspi_disable_bspi(qspi);
833 dev_err(&qspi->pdev->dev, "%s: too many slots!\n", __func__);
837 tp = qspi->trans_pos;
844 buf[tp.byte] = read_rxram_slot_u8(qspi, slot);
845 dev_dbg(&qspi->pdev->dev, "RD %02x\n",
851 buf[tp.byte / 2] = read_rxram_slot_u16(qspi,
853 dev_dbg(&qspi->pdev->dev, "RD %04x\n",
859 buf[tp.byte / 4] = read_rxram_slot_u32(qspi,
861 dev_dbg(&qspi->pdev->dev, "RD %08x\n",
868 buf[tp.byte / 8] = read_rxram_slot_u64(qspi,
870 dev_dbg(&qspi->pdev->dev, "RD %llx\n",
876 update_qspi_trans_byte_count(qspi, &tp,
880 qspi->trans_pos = tp;
883 static inline void write_txram_slot_u8(struct bcm_qspi *qspi, int slot,
889 bcm_qspi_write(qspi, MSPI, reg_offset, val);
892 static inline void write_txram_slot_u16(struct bcm_qspi *qspi, int slot,
899 bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8));
900 bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff));
903 static inline void write_txram_slot_u32(struct bcm_qspi *qspi, int slot,
909 bcm_qspi_write(qspi, MSPI, msb_offset, swap4bytes(val));
912 static inline void write_txram_slot_u64(struct bcm_qspi *qspi, int slot,
921 bcm_qspi_write(qspi, MSPI, msb_offset, swap4bytes(msb));
922 bcm_qspi_write(qspi, MSPI, lsb_offset, swap4bytes(lsb));
925 static inline u32 read_cdram_slot(struct bcm_qspi *qspi, int slot)
927 return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2));
930 static inline void write_cdram_slot(struct bcm_qspi *qspi, int slot, u32 val)
932 bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val);
936 static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
942 bcm_qspi_disable_bspi(qspi);
943 tp = qspi->trans_pos;
944 bcm_qspi_update_parms(qspi, spi, tp.trans);
953 write_txram_slot_u8(qspi, slot, val);
954 dev_dbg(&qspi->pdev->dev, "WR %02x\n", val);
959 write_txram_slot_u16(qspi, slot, val);
960 dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
965 write_txram_slot_u32(qspi, slot, val);
966 dev_dbg(&qspi->pdev->dev, "WR %08x\n", val);
972 if (bcm_qspi_has_fastbr(qspi))
975 write_txram_slot_u64(qspi, slot, val);
976 dev_dbg(&qspi->pdev->dev, "WR %llx\n", val);
986 if (has_bspi(qspi))
992 write_cdram_slot(qspi, slot, mspi_cdram);
994 tstatus = update_qspi_trans_byte_count(qspi, &tp,
1000 dev_err(&qspi->pdev->dev, "%s: no data to send?", __func__);
1004 dev_dbg(&qspi->pdev->dev, "submitting %d slots\n", slot);
1005 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
1006 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);
1018 mspi_cdram = read_cdram_slot(qspi, slot - 1) &
1020 write_cdram_slot(qspi, slot - 1, mspi_cdram);
1023 if (has_bspi(qspi))
1024 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 1);
1029 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0);
1038 struct bcm_qspi *qspi = spi_controller_get_devdata(spi->controller);
1042 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1044 if (bcm_qspi_bspi_ver_three(qspi))
1050 bcm_qspi_chip_select(qspi, spi_get_chipselect(spi, 0));
1051 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
1057 if (!bcm_qspi_bspi_ver_three(qspi)) {
1059 bcm_qspi_write(qspi, BSPI,
1063 if (!qspi->xfer_mode.flex_mode)
1068 if (bcm_qspi_bspi_ver_three(qspi) == true)
1076 qspi->bspi_rf_op_idx = 0;
1084 reinit_completion(&qspi->bspi_done);
1085 bcm_qspi_enable_bspi(qspi);
1087 qspi->bspi_rf_op = op;
1088 qspi->bspi_rf_op_status = 0;
1089 qspi->bspi_rf_op_len = rdlen;
1090 dev_dbg(&qspi->pdev->dev,
1092 bcm_qspi_write(qspi, BSPI, BSPI_RAF_START_ADDR, addr);
1093 bcm_qspi_write(qspi, BSPI, BSPI_RAF_NUM_WORDS, len_words);
1094 bcm_qspi_write(qspi, BSPI, BSPI_RAF_WATERMARK, 0);
1095 if (qspi->soc_intc) {
1106 bcm_qspi_bspi_lr_start(qspi);
1107 if (!wait_for_completion_timeout(&qspi->bspi_done, timeo)) {
1108 dev_err(&qspi->pdev->dev, "timeout waiting for BSPI\n");
1125 struct bcm_qspi *qspi = spi_controller_get_devdata(host);
1130 bcm_qspi_chip_select(qspi, spi_get_chipselect(spi, 0));
1131 qspi->trans_pos.trans = trans;
1132 qspi->trans_pos.byte = 0;
1134 while (qspi->trans_pos.byte < trans->len) {
1135 reinit_completion(&qspi->mspi_done);
1137 slots = write_to_hw(qspi, spi);
1138 if (!wait_for_completion_timeout(&qspi->mspi_done, timeo)) {
1139 dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n");
1143 read_from_hw(qspi, slots);
1145 bcm_qspi_enable_bspi(qspi);
1154 struct bcm_qspi *qspi = spi_controller_get_devdata(host);
1173 qspi->trans_pos.mspi_last_trans = false;
1177 qspi->trans_pos.mspi_last_trans = true;
1194 struct bcm_qspi *qspi = spi_controller_get_devdata(spi->controller);
1208 if (has_bspi(qspi) && bcm_qspi_bspi_ver_three(qspi) == true) {
1227 if (!has_bspi(qspi) || mspi_read)
1230 ret = bcm_qspi_bspi_set_mode(qspi, op, 0);
1248 struct bcm_qspi *qspi = qspi_dev_id->dev;
1249 u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
1252 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1255 bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status);
1256 if (qspi->soc_intc)
1258 complete(&qspi->mspi_done);
1268 struct bcm_qspi *qspi = qspi_dev_id->dev;
1269 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1272 if (qspi->bspi_enabled && qspi->bspi_rf_op) {
1273 bcm_qspi_bspi_lr_data_read(qspi);
1274 if (qspi->bspi_rf_op_len == 0) {
1275 qspi->bspi_rf_op = NULL;
1276 if (qspi->soc_intc) {
1284 if (qspi->bspi_rf_op_status)
1285 bcm_qspi_bspi_lr_clear(qspi);
1287 bcm_qspi_bspi_flush_prefetch_buffers(qspi);
1290 if (qspi->soc_intc)
1296 if (qspi->bspi_enabled && status && qspi->bspi_rf_op_len == 0)
1297 complete(&qspi->bspi_done);
1305 struct bcm_qspi *qspi = qspi_dev_id->dev;
1306 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1308 dev_err(&qspi->pdev->dev, "BSPI INT error\n");
1309 qspi->bspi_rf_op_status = -EIO;
1310 if (qspi->soc_intc)
1314 complete(&qspi->bspi_done);
1321 struct bcm_qspi *qspi = qspi_dev_id->dev;
1322 struct bcm_qspi_soc_intc *soc_intc = qspi->soc_intc;
1387 static void bcm_qspi_bspi_init(struct bcm_qspi *qspi)
1391 val = bcm_qspi_read(qspi, BSPI, BSPI_REVISION_ID);
1392 qspi->bspi_maj_rev = (val >> 8) & 0xff;
1393 qspi->bspi_min_rev = val & 0xff;
1394 if (!(bcm_qspi_bspi_ver_three(qspi))) {
1396 bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_VALUE, 0);
1397 bcm_qspi_write(qspi, BSPI, BSPI_BSPI_XOR_ENABLE, 1);
1399 qspi->bspi_enabled = 1;
1400 bcm_qspi_disable_bspi(qspi);
1401 bcm_qspi_write(qspi, BSPI, BSPI_B0_CTRL, 0);
1402 bcm_qspi_write(qspi, BSPI, BSPI_B1_CTRL, 0);
1405 static void bcm_qspi_hw_init(struct bcm_qspi *qspi)
1409 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0);
1410 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0);
1411 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
1412 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0);
1413 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20);
1417 parms.speed_hz = qspi->max_speed_hz;
1418 bcm_qspi_hw_set_parms(qspi, &parms);
1420 if (has_bspi(qspi))
1421 bcm_qspi_bspi_init(qspi);
1424 static void bcm_qspi_hw_uninit(struct bcm_qspi *qspi)
1426 u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
1428 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0);
1429 if (has_bspi(qspi))
1430 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
1433 bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status & ~1);
1462 .compatible = "brcm,spi-bcm7445-qspi",
1467 .compatible = "brcm,spi-bcm-qspi",
1471 .compatible = "brcm,spi-bcm7216-qspi",
1475 .compatible = "brcm,spi-bcm7278-qspi",
1488 struct bcm_qspi *qspi;
1513 qspi = spi_controller_get_devdata(host);
1515 qspi->clk = devm_clk_get_optional(&pdev->dev, NULL);
1516 if (IS_ERR(qspi->clk))
1517 return PTR_ERR(qspi->clk);
1519 qspi->pdev = pdev;
1520 qspi->trans_pos.trans = NULL;
1521 qspi->trans_pos.byte = 0;
1522 qspi->trans_pos.mspi_last_trans = true;
1523 qspi->host = host;
1536 qspi->big_endian = of_device_is_big_endian(dev->of_node);
1546 qspi->base[MSPI] = devm_ioremap_resource(dev, res);
1547 if (IS_ERR(qspi->base[MSPI]))
1548 return PTR_ERR(qspi->base[MSPI]);
1552 qspi->base[BSPI] = devm_ioremap_resource(dev, res);
1553 if (IS_ERR(qspi->base[BSPI]))
1554 return PTR_ERR(qspi->base[BSPI]);
1555 qspi->bspi_mode = true;
1557 qspi->bspi_mode = false;
1560 dev_info(dev, "using %smspi mode\n", qspi->bspi_mode ? "bspi-" : "");
1564 qspi->base[CHIP_SELECT] = devm_ioremap_resource(dev, res);
1565 if (IS_ERR(qspi->base[CHIP_SELECT]))
1566 return PTR_ERR(qspi->base[CHIP_SELECT]);
1569 qspi->dev_ids = kcalloc(num_irqs, sizeof(struct bcm_qspi_dev_id),
1571 if (!qspi->dev_ids)
1579 qspi->soc_intc = soc_intc;
1582 qspi->soc_intc = NULL;
1585 if (qspi->clk) {
1586 ret = clk_prepare_enable(qspi->clk);
1591 qspi->base_clk = clk_get_rate(qspi->clk);
1593 qspi->base_clk = MSPI_BASE_FREQ;
1597 rev = bcm_qspi_read(qspi, MSPI, MSPI_REV);
1603 qspi->mspi_maj_rev = (rev >> 4) & 0xf;
1604 qspi->mspi_min_rev = rev & 0xf;
1605 qspi->mspi_spcr3_sysclk = data->has_spcr3_sysclk;
1607 qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2);
1613 bcm_qspi_hw_uninit(qspi);
1630 &qspi->dev_ids[val]);
1636 qspi->dev_ids[val].dev = qspi;
1637 qspi->dev_ids[val].irqp = &qspi_irq_tab[val];
1651 bcm_qspi_hw_init(qspi);
1652 init_completion(&qspi->mspi_done);
1653 init_completion(&qspi->bspi_done);
1654 qspi->curr_cs = -1;
1656 platform_set_drvdata(pdev, qspi);
1658 qspi->xfer_mode.width = -1;
1659 qspi->xfer_mode.addrlen = -1;
1660 qspi->xfer_mode.hp = -1;
1671 bcm_qspi_hw_uninit(qspi);
1673 clk_disable_unprepare(qspi->clk);
1675 kfree(qspi->dev_ids);
1683 struct bcm_qspi *qspi = platform_get_drvdata(pdev);
1685 spi_unregister_controller(qspi->host);
1686 bcm_qspi_hw_uninit(qspi);
1687 clk_disable_unprepare(qspi->clk);
1688 kfree(qspi->dev_ids);
1696 struct bcm_qspi *qspi = dev_get_drvdata(dev);
1699 if (!bcm_qspi_bspi_ver_three(qspi))
1700 qspi->s3_strap_override_ctrl =
1701 bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
1703 spi_controller_suspend(qspi->host);
1704 clk_disable_unprepare(qspi->clk);
1705 bcm_qspi_hw_uninit(qspi);
1712 struct bcm_qspi *qspi = dev_get_drvdata(dev);
1715 bcm_qspi_hw_init(qspi);
1716 bcm_qspi_chip_select(qspi, qspi->curr_cs);
1717 if (qspi->soc_intc)
1719 qspi->soc_intc->bcm_qspi_int_set(qspi->soc_intc, MSPI_DONE,
1722 ret = clk_prepare_enable(qspi->clk);
1724 spi_controller_resume(qspi->host);