Lines Matching defs:MSPI
83 /* MSPI register offsets */
191 MSPI,
610 /* MSPI helpers */
636 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
670 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 1);
681 bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr);
688 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spbr);
784 return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff;
793 return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) |
794 ((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8);
803 val = bcm_qspi_read(qspi, MSPI, offset);
816 msb = bcm_qspi_read(qspi, MSPI, msb_offset);
818 lsb = bcm_qspi_read(qspi, MSPI, lsb_offset);
889 bcm_qspi_write(qspi, MSPI, reg_offset, val);
899 bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8));
900 bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff));
909 bcm_qspi_write(qspi, MSPI, msb_offset, swap4bytes(val));
921 bcm_qspi_write(qspi, MSPI, msb_offset, swap4bytes(msb));
922 bcm_qspi_write(qspi, MSPI, lsb_offset, swap4bytes(lsb));
927 return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2));
932 bcm_qspi_write(qspi, MSPI, (MSPI_CDRAM + (slot << 2)), val);
1005 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
1006 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);
1024 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 1);
1026 /* Must flush previous writes before starting MSPI operation */
1029 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0xe0);
1051 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
1097 * clear soc MSPI and BSPI interrupts and enable
1139 dev_err(&qspi->pdev->dev, "timeout waiting for MSPI\n");
1213 * using MSPI.
1222 /* non-aligned and very short transfers are handled by MSPI */
1249 u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
1255 bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status);
1409 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_LSB, 0);
1410 bcm_qspi_write(qspi, MSPI, MSPI_SPCR1_MSB, 0);
1411 bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
1412 bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, 0);
1413 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0x20);
1426 u32 status = bcm_qspi_read(qspi, MSPI, MSPI_MSPI_STATUS);
1428 bcm_qspi_write(qspi, MSPI, MSPI_SPCR2, 0);
1430 bcm_qspi_write(qspi, MSPI, MSPI_WRITE_LOCK, 0);
1433 bcm_qspi_write(qspi, MSPI, MSPI_MSPI_STATUS, status & ~1);
1546 qspi->base[MSPI] = devm_ioremap_resource(dev, res);
1547 if (IS_ERR(qspi->base[MSPI]))
1548 return PTR_ERR(qspi->base[MSPI]);
1597 rev = bcm_qspi_read(qspi, MSPI, MSPI_REV);
1718 /* enable MSPI interrupt */