Lines Matching refs:hw
52 void (*rx_word)(struct au1550_spi *hw);
53 void (*tx_word)(struct au1550_spi *hw);
55 irqreturn_t (*irq_callback)(struct au1550_spi *hw);
89 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
101 static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned int speed_hz)
103 u32 mainclk_hz = hw->pdata->mainclk_hz;
124 static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
126 hw->regs->psc_spimsk =
132 hw->regs->psc_spievent =
139 static void au1550_spi_reset_fifos(struct au1550_spi *hw)
143 hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
146 pcr = hw->regs->psc_spipcr;
162 struct au1550_spi *hw = spi_controller_get_devdata(spi->controller);
168 if (hw->pdata->deactivate_cs)
169 hw->pdata->deactivate_cs(hw->pdata, spi_get_chipselect(spi, 0),
174 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
176 cfg = hw->regs->psc_spicfg;
178 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
195 if (hw->usedma && spi->bits_per_word <= 8)
204 cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
206 hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
209 stat = hw->regs->psc_spistat;
213 if (hw->pdata->activate_cs)
214 hw->pdata->activate_cs(hw->pdata, spi_get_chipselect(spi, 0),
222 struct au1550_spi *hw = spi_controller_get_devdata(spi->controller);
237 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
239 cfg = hw->regs->psc_spicfg;
241 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
244 if (hw->usedma && bpw <= 8)
253 cfg |= au1550_spi_baudcfg(hw, hz);
255 hw->regs->psc_spicfg = cfg;
260 stat = hw->regs->psc_spistat;
265 au1550_spi_reset_fifos(hw);
266 au1550_spi_mask_ack_all(hw);
278 static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned int size)
280 hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
281 if (!hw->dma_rx_tmpbuf)
283 hw->dma_rx_tmpbuf_size = size;
284 hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf,
286 if (dma_mapping_error(hw->dev, hw->dma_rx_tmpbuf_addr)) {
287 kfree(hw->dma_rx_tmpbuf);
288 hw->dma_rx_tmpbuf = 0;
289 hw->dma_rx_tmpbuf_size = 0;
295 static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw)
297 dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr,
298 hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE);
299 kfree(hw->dma_rx_tmpbuf);
300 hw->dma_rx_tmpbuf = 0;
301 hw->dma_rx_tmpbuf_size = 0;
306 struct au1550_spi *hw = spi_controller_get_devdata(spi->controller);
311 hw->len = t->len;
312 hw->tx_count = 0;
313 hw->rx_count = 0;
315 hw->tx = t->tx_buf;
316 hw->rx = t->rx_buf;
330 dma_tx_addr = dma_map_single(hw->dev,
333 if (dma_mapping_error(hw->dev, dma_tx_addr))
334 dev_err(hw->dev, "tx dma map error\n");
340 dma_rx_addr = dma_map_single(hw->dev,
343 if (dma_mapping_error(hw->dev, dma_rx_addr))
344 dev_err(hw->dev, "rx dma map error\n");
347 if (t->len > hw->dma_rx_tmpbuf_size) {
350 au1550_spi_dma_rxtmp_free(hw);
351 ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len,
356 hw->rx = hw->dma_rx_tmpbuf;
357 dma_rx_addr = hw->dma_rx_tmpbuf_addr;
358 dma_sync_single_for_device(hw->dev, dma_rx_addr,
363 dma_sync_single_for_device(hw->dev, dma_rx_addr,
365 hw->tx = hw->rx;
369 res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, virt_to_phys(hw->rx),
372 dev_err(hw->dev, "rx dma put dest error\n");
374 res = au1xxx_dbdma_put_source(hw->dma_tx_ch, virt_to_phys(hw->tx),
377 dev_err(hw->dev, "tx dma put source error\n");
379 au1xxx_dbdma_start(hw->dma_rx_ch);
380 au1xxx_dbdma_start(hw->dma_tx_ch);
383 hw->regs->psc_spimsk = PSC_SPIMSK_SD;
387 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
390 wait_for_completion(&hw->host_done);
392 au1xxx_dbdma_stop(hw->dma_tx_ch);
393 au1xxx_dbdma_stop(hw->dma_rx_ch);
397 dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len,
402 dma_unmap_single(hw->dev, dma_rx_addr, t->len,
405 dma_unmap_single(hw->dev, dma_tx_addr, t->len,
408 return min(hw->rx_count, hw->tx_count);
411 static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
415 stat = hw->regs->psc_spistat;
416 evnt = hw->regs->psc_spievent;
419 dev_err(hw->dev, "Unexpected IRQ!\n");
432 au1550_spi_mask_ack_all(hw);
433 au1xxx_dbdma_stop(hw->dma_rx_ch);
434 au1xxx_dbdma_stop(hw->dma_tx_ch);
437 hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch);
438 hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch);
440 au1xxx_dbdma_reset(hw->dma_rx_ch);
441 au1xxx_dbdma_reset(hw->dma_tx_ch);
442 au1550_spi_reset_fifos(hw);
445 dev_err(hw->dev,
448 dev_err(hw->dev,
452 complete(&hw->host_done);
458 au1550_spi_mask_ack_all(hw);
459 hw->rx_count = hw->len;
460 hw->tx_count = hw->len;
461 complete(&hw->host_done);
469 static void au1550_spi_rx_word_##size(struct au1550_spi *hw) \
471 u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask); \
473 if (hw->rx) { \
474 *(u##size *)hw->rx = (u##size)fifoword; \
475 hw->rx += (size) / 8; \
477 hw->rx_count += (size) / 8; \
481 static void au1550_spi_tx_word_##size(struct au1550_spi *hw) \
484 if (hw->tx) { \
485 fifoword = *(u##size *)hw->tx & (u32)(mask); \
486 hw->tx += (size) / 8; \
488 hw->tx_count += (size) / 8; \
489 if (hw->tx_count >= hw->len) \
491 hw->regs->psc_spitxrx = fifoword; \
505 struct au1550_spi *hw = spi_controller_get_devdata(spi->controller);
507 hw->tx = t->tx_buf;
508 hw->rx = t->rx_buf;
509 hw->len = t->len;
510 hw->tx_count = 0;
511 hw->rx_count = 0;
517 while (hw->tx_count < hw->len) {
519 hw->tx_word(hw);
521 if (hw->tx_count >= hw->len) {
526 stat = hw->regs->psc_spistat;
533 hw->regs->psc_spimsk = mask;
537 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
540 wait_for_completion(&hw->host_done);
542 return min(hw->rx_count, hw->tx_count);
545 static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
550 stat = hw->regs->psc_spistat;
551 evnt = hw->regs->psc_spievent;
554 dev_err(hw->dev, "Unexpected IRQ!\n");
566 au1550_spi_mask_ack_all(hw);
567 au1550_spi_reset_fifos(hw);
568 dev_err(hw->dev,
571 complete(&hw->host_done);
581 stat = hw->regs->psc_spistat;
593 if (!(stat & PSC_SPISTAT_RE) && hw->rx_count < hw->len) {
594 hw->rx_word(hw);
597 if (!(stat & PSC_SPISTAT_TF) && hw->tx_count < hw->len)
598 hw->tx_word(hw);
602 hw->regs->psc_spievent = PSC_SPIEVNT_RR | PSC_SPIEVNT_TR;
621 hw->regs->psc_spievent = PSC_SPIEVNT_TU | PSC_SPIEVNT_MD;
623 hw->regs->psc_spipcr = PSC_SPIPCR_MS;
627 if (hw->rx_count >= hw->len) {
629 au1550_spi_mask_ack_all(hw);
630 complete(&hw->host_done);
637 struct au1550_spi *hw = spi_controller_get_devdata(spi->controller);
639 return hw->txrx_bufs(spi, t);
644 struct au1550_spi *hw = dev;
646 return hw->irq_callback(hw);
649 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw)
652 if (hw->usedma) {
653 hw->txrx_bufs = &au1550_spi_dma_txrxb;
654 hw->irq_callback = &au1550_spi_dma_irq_callback;
656 hw->rx_word = &au1550_spi_rx_word_8;
657 hw->tx_word = &au1550_spi_tx_word_8;
658 hw->txrx_bufs = &au1550_spi_pio_txrxb;
659 hw->irq_callback = &au1550_spi_pio_irq_callback;
662 hw->rx_word = &au1550_spi_rx_word_16;
663 hw->tx_word = &au1550_spi_tx_word_16;
664 hw->txrx_bufs = &au1550_spi_pio_txrxb;
665 hw->irq_callback = &au1550_spi_pio_irq_callback;
667 hw->rx_word = &au1550_spi_rx_word_32;
668 hw->tx_word = &au1550_spi_tx_word_32;
669 hw->txrx_bufs = &au1550_spi_pio_txrxb;
670 hw->irq_callback = &au1550_spi_pio_irq_callback;
674 static void au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
679 hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
681 hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
684 hw->regs->psc_spicfg = 0;
687 hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
691 stat = hw->regs->psc_spistat;
696 cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE;
706 hw->regs->psc_spicfg = cfg;
709 au1550_spi_mask_ack_all(hw);
711 hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
715 stat = hw->regs->psc_spistat;
719 au1550_spi_reset_fifos(hw);
725 struct au1550_spi *hw;
741 hw = spi_controller_get_devdata(host);
743 hw->host = host;
744 hw->pdata = dev_get_platdata(&pdev->dev);
745 hw->dev = &pdev->dev;
747 if (hw->pdata == NULL) {
759 hw->irq = r->start;
761 hw->usedma = 0;
764 hw->dma_tx_id = r->start;
767 hw->dma_rx_id = r->start;
772 hw->usedma = 1;
784 hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t),
786 if (!hw->ioarea) {
792 hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t));
793 if (!hw->regs) {
799 platform_set_drvdata(pdev, hw);
801 init_completion(&hw->host_done);
803 hw->bitbang.master = hw->host;
804 hw->bitbang.setup_transfer = au1550_spi_setupxfer;
805 hw->bitbang.chipselect = au1550_spi_chipsel;
806 hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
808 if (hw->usedma) {
809 hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid,
810 hw->dma_tx_id, NULL, (void *)hw);
811 if (hw->dma_tx_ch == 0) {
817 au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8);
818 if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch,
827 hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
828 ddma_memid, NULL, (void *)hw);
829 if (hw->dma_rx_ch == 0) {
835 au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8);
836 if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch,
844 err = au1550_spi_dma_rxtmp_alloc(hw,
853 au1550_spi_bits_handlers_set(hw, 8);
855 err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw);
862 host->num_chipselect = hw->pdata->num_chipselect;
877 host->max_speed_hz = hw->pdata->mainclk_hz / min_div;
879 hw->pdata->mainclk_hz / (max_div + 1) + 1;
882 au1550_spi_setup_psc_as_spi(hw);
884 err = spi_bitbang_start(&hw->bitbang);
897 free_irq(hw->irq, hw);
900 au1550_spi_dma_rxtmp_free(hw);
904 if (hw->usedma)
905 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
909 if (hw->usedma)
910 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
913 iounmap((void __iomem *)hw->regs);
920 spi_controller_put(hw->host);
928 struct au1550_spi *hw = platform_get_drvdata(pdev);
931 hw->host->bus_num);
933 spi_bitbang_stop(&hw->bitbang);
934 free_irq(hw->irq, hw);
935 iounmap((void __iomem *)hw->regs);
936 release_mem_region(hw->ioarea->start, sizeof(psc_spi_t));
938 if (hw->usedma) {
939 au1550_spi_dma_rxtmp_free(hw);
940 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
941 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
944 spi_controller_put(hw->host);