Lines Matching defs:brg
104 u32 div, brg;
107 brg = mainclk_hz / speed_hz / (4 << div);
108 /* now we have BRG+1 in brg, so count with that */
109 if (brg < (4 + 1)) {
110 brg = (4 + 1); /* speed_hz too big */
111 break; /* set lowest brg (div is == 0) */
113 if (brg <= (63 + 1))
114 break; /* we have valid brg and div */
118 brg = (63 + 1); /* set highest brg and div */
120 brg--;
121 return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
699 /* use minimal allowed brg and div values as initial setting: */
871 * produce valid brg and div