Lines Matching refs:data
306 * 8 bits is the minimum data the controller is capable of sending.
339 * the controller to send the data.
346 * Read all data coming from SPI bus, needed to be able to send
365 * that automagic deselection is OK. ("NPCSx rises if no data is to be
542 * In this mode, up to 2 data, not 4, can be written into the Transmit
544 * However, the first data has to be written into the lowest 16 bits and
545 * the second data into the highest 16 bits of the Transmit
546 * Data Register. For 8bit data (the most frequent case), it would
547 * require to rework tx_buf so each data would actually fit 16 bits.
548 * So we'd rather write only one data at the time. Hence the transmit
639 static void dma_callback(void *data)
641 struct spi_controller *host = data;
663 /* Make sure data is not remaining in RDR */
700 /* Compute the number of data to transfer in the current iteration */
711 /* Set RX FIFO Threshold to the number of data to transfer */
1088 /* Handle odd number of bytes when data are more than 8bit width */
1092 /* Read data */
1105 * Must update "current_remaining_bytes" to keep track of data
1436 * Clean up DMA registers and make sure the data
1640 dev_info(&pdev->dev, "Using FIFO (%u data)\n", as->fifo_size);