Lines Matching defs:aus
106 struct at91_usart_spi *aus = spi_controller_get_devdata(ctlr);
108 at91_usart_spi_writel(aus, IER, US_IR_RXRDY);
109 aus->current_rx_remaining_bytes = 0;
110 complete(&aus->xfer_completion);
117 struct at91_usart_spi *aus = spi_controller_get_devdata(ctrl);
119 return aus->use_dma && xfer->len >= US_DMA_MIN_BYTES;
123 struct at91_usart_spi *aus)
126 struct device *dev = &aus->mpdev->dev;
127 phys_addr_t phybase = aus->phybase;
184 aus->use_dma = true;
218 struct at91_usart_spi *aus = spi_controller_get_devdata(ctlr);
226 at91_usart_spi_writel(aus, IDR, US_IR_RXRDY);
264 at91_usart_spi_writel(aus, IER, US_IR_RXRDY);
270 static unsigned long at91_usart_spi_dma_timeout(struct at91_usart_spi *aus)
272 return wait_for_completion_timeout(&aus->xfer_completion,
276 static inline u32 at91_usart_spi_tx_ready(struct at91_usart_spi *aus)
278 return aus->status & US_IR_TXRDY;
281 static inline u32 at91_usart_spi_rx_ready(struct at91_usart_spi *aus)
283 return aus->status & US_IR_RXRDY;
286 static inline u32 at91_usart_spi_check_overrun(struct at91_usart_spi *aus)
288 return aus->status & US_IR_OVRE;
291 static inline u32 at91_usart_spi_read_status(struct at91_usart_spi *aus)
293 aus->status = at91_usart_spi_readl(aus, CSR);
294 return aus->status;
297 static inline void at91_usart_spi_tx(struct at91_usart_spi *aus)
299 unsigned int len = aus->current_transfer->len;
300 unsigned int remaining = aus->current_tx_remaining_bytes;
301 const u8 *tx_buf = aus->current_transfer->tx_buf;
306 if (at91_usart_spi_tx_ready(aus)) {
307 at91_usart_spi_writeb(aus, THR, tx_buf[len - remaining]);
308 aus->current_tx_remaining_bytes--;
312 static inline void at91_usart_spi_rx(struct at91_usart_spi *aus)
314 int len = aus->current_transfer->len;
315 int remaining = aus->current_rx_remaining_bytes;
316 u8 *rx_buf = aus->current_transfer->rx_buf;
321 rx_buf[len - remaining] = at91_usart_spi_readb(aus, RHR);
322 aus->current_rx_remaining_bytes--;
326 at91_usart_spi_set_xfer_speed(struct at91_usart_spi *aus,
329 at91_usart_spi_writel(aus, BRGR,
330 DIV_ROUND_UP(aus->spi_clk, xfer->speed_hz));
336 struct at91_usart_spi *aus = spi_controller_get_devdata(controller);
338 spin_lock(&aus->lock);
339 at91_usart_spi_read_status(aus);
341 if (at91_usart_spi_check_overrun(aus)) {
342 aus->xfer_failed = true;
343 at91_usart_spi_writel(aus, IDR, US_IR_OVRE | US_IR_RXRDY);
344 spin_unlock(&aus->lock);
348 if (at91_usart_spi_rx_ready(aus)) {
349 at91_usart_spi_rx(aus);
350 spin_unlock(&aus->lock);
354 spin_unlock(&aus->lock);
361 struct at91_usart_spi *aus = spi_controller_get_devdata(spi->controller);
363 unsigned int mr = at91_usart_spi_readl(aus, MR);
401 struct at91_usart_spi *aus = spi_controller_get_devdata(ctlr);
405 at91_usart_spi_set_xfer_speed(aus, xfer);
406 aus->xfer_failed = false;
407 aus->current_transfer = xfer;
408 aus->current_tx_remaining_bytes = xfer->len;
409 aus->current_rx_remaining_bytes = xfer->len;
411 while ((aus->current_tx_remaining_bytes ||
412 aus->current_rx_remaining_bytes) && !aus->xfer_failed) {
413 reinit_completion(&aus->xfer_completion);
420 dma_timeout = at91_usart_spi_dma_timeout(aus);
426 aus->current_tx_remaining_bytes = 0;
428 at91_usart_spi_read_status(aus);
429 at91_usart_spi_tx(aus);
435 if (aus->xfer_failed) {
436 dev_err(aus->dev, "Overrun!\n");
446 struct at91_usart_spi *aus = spi_controller_get_devdata(ctlr);
450 at91_usart_spi_writel(aus, CR, US_ENABLE);
451 at91_usart_spi_writel(aus, IER, US_OVRE_RXRDY_IRQS);
452 at91_usart_spi_writel(aus, MR, *ausd);
460 struct at91_usart_spi *aus = spi_controller_get_devdata(ctlr);
462 at91_usart_spi_writel(aus, CR, US_RESET | US_DISABLE);
463 at91_usart_spi_writel(aus, IDR, US_OVRE_RXRDY_IRQS);
476 static void at91_usart_spi_init(struct at91_usart_spi *aus)
478 at91_usart_spi_writel(aus, MR, US_INIT);
479 at91_usart_spi_writel(aus, CR, US_RESET | US_DISABLE);
495 struct at91_usart_spi *aus;
514 controller = spi_alloc_host(&pdev->dev, sizeof(*aus));
538 aus = spi_controller_get_devdata(controller);
540 aus->dev = &pdev->dev;
541 aus->regs = devm_ioremap_resource(&pdev->dev, regs);
542 if (IS_ERR(aus->regs)) {
543 ret = PTR_ERR(aus->regs);
547 aus->irq = irq;
548 aus->clk = clk;
559 aus->spi_clk = clk_get_rate(clk);
560 at91_usart_spi_init(aus);
562 aus->phybase = regs->start;
564 aus->mpdev = to_platform_device(pdev->dev.parent);
566 ret = at91_usart_spi_configure_dma(controller, aus);
570 spin_lock_init(&aus->lock);
571 init_completion(&aus->xfer_completion);
579 at91_usart_spi_readl(aus, VERSION),
596 struct at91_usart_spi *aus = spi_controller_get_devdata(ctlr);
598 clk_disable_unprepare(aus->clk);
607 struct at91_usart_spi *aus = spi_controller_get_devdata(ctrl);
611 return clk_prepare_enable(aus->clk);
632 struct at91_usart_spi *aus = spi_controller_get_devdata(ctrl);
641 at91_usart_spi_init(aus);
649 struct at91_usart_spi *aus = spi_controller_get_devdata(ctlr);
652 clk_disable_unprepare(aus->clk);