Lines Matching refs:aspi
63 struct aspeed_spi *aspi;
82 u32 (*segment_start)(struct aspeed_spi *aspi, u32 reg);
83 u32 (*segment_end)(struct aspeed_spi *aspi, u32 reg);
84 u32 (*segment_reg)(struct aspeed_spi *aspi, u32 start, u32 end);
298 struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->controller);
299 struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(mem->spi, 0)];
304 dev_dbg(aspi->dev,
311 addr_mode = readl(aspi->regs + CE_CTRL_REG);
326 if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
342 writel(addr_mode, aspi->regs + CE_CTRL_REG);
360 writel(addr_mode_backup, aspi->regs + CE_CTRL_REG);
377 struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->controller);
378 struct device *dev = aspi->dev;
390 static void aspeed_spi_get_windows(struct aspeed_spi *aspi,
393 const struct aspeed_spi_data *data = aspi->data;
397 for (cs = 0; cs < aspi->data->max_cs; cs++) {
398 reg_val = readl(aspi->regs + CE0_SEGMENT_ADDR_REG + cs * 4);
400 windows[cs].size = data->segment_end(aspi, reg_val) -
401 data->segment_start(aspi, reg_val);
402 windows[cs].offset = data->segment_start(aspi, reg_val) - aspi->ahb_base_phy;
403 dev_vdbg(aspi->dev, "CE%d offset=0x%.8x size=0x%x\n", cs,
414 struct aspeed_spi *aspi = chip->aspi;
419 if (aspi->data == &ast2400_spi_data) {
421 win->size = aspi->ahb_window_size;
423 aspeed_spi_get_windows(aspi, windows);
426 chip->ahb_base = aspi->ahb_base + win->offset;
429 dev_dbg(aspi->dev, "CE%d default window [ 0x%.8x - 0x%.8x ] %dMB",
430 chip->cs, aspi->ahb_base_phy + win->offset,
431 aspi->ahb_base_phy + win->offset + win->size - 1,
437 static int aspeed_spi_set_window(struct aspeed_spi *aspi,
440 u32 start = aspi->ahb_base_phy + win->offset;
442 void __iomem *seg_reg = aspi->regs + CE0_SEGMENT_ADDR_REG + win->cs * 4;
444 u32 seg_val = aspi->data->segment_reg(aspi, start, end);
456 dev_err(aspi->dev, "CE%d invalid window [ 0x%.8x - 0x%.8x ] %dMB",
463 dev_dbg(aspi->dev, "CE%d new window [ 0x%.8x - 0x%.8x ] %dMB",
466 dev_dbg(aspi->dev, "CE%d window closed", win->cs);
484 struct aspeed_spi *aspi = chip->aspi;
490 if (aspi->data == &ast2400_spi_data)
497 if (aspi->data == &ast2500_spi_data && chip->cs == 0 && size == SZ_128M) {
499 dev_info(aspi->dev, "CE%d window resized to %dMB (AST2500 HW quirk)",
507 if ((aspi->data == &ast2600_spi_data || aspi->data == &ast2600_fmc_data) &&
510 dev_info(aspi->dev, "CE%d window resized to %dMB (AST2600 Decoding)",
514 aspeed_spi_get_windows(aspi, windows);
520 if (win->offset + win->size > aspi->ahb_window_size) {
521 win->size = aspi->ahb_window_size - win->offset;
522 dev_warn(aspi->dev, "CE%d window resized to %dMB", chip->cs, win->size >> 20);
525 ret = aspeed_spi_set_window(aspi, win);
530 chip->ahb_base = aspi->ahb_base + win->offset;
537 if (chip->cs < aspi->data->max_cs - 1) {
547 aspeed_spi_set_window(aspi, next);
556 struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->controller);
557 struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(desc->mem->spi, 0)];
562 dev_dbg(aspi->dev,
579 dev_warn(aspi->dev, "CE%d window (%dMB) too small for mapping",
593 u32 addr_mode = readl(aspi->regs + CE_CTRL_REG);
599 writel(addr_mode, aspi->regs + CE_CTRL_REG);
604 if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data)
614 dev_info(aspi->dev, "CE%d read buswidth:%d [0x%08x]\n",
623 struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->controller);
624 struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(desc->mem->spi, 0)];
648 static void aspeed_spi_chip_set_type(struct aspeed_spi *aspi, unsigned int cs, int type)
652 reg = readl(aspi->regs + CONFIG_REG);
655 writel(reg, aspi->regs + CONFIG_REG);
658 static void aspeed_spi_chip_enable(struct aspeed_spi *aspi, unsigned int cs, bool enable)
660 u32 we_bit = BIT(aspi->data->we0 + cs);
661 u32 reg = readl(aspi->regs + CONFIG_REG);
667 writel(reg, aspi->regs + CONFIG_REG);
672 struct aspeed_spi *aspi = spi_controller_get_devdata(spi->controller);
673 const struct aspeed_spi_data *data = aspi->data;
675 struct aspeed_spi_chip *chip = &aspi->chips[cs];
677 chip->aspi = aspi;
679 chip->ctl = aspi->regs + data->ctl0 + cs * 4;
683 aspeed_spi_chip_set_type(aspi, cs, CONFIG_TYPE_SPI);
686 dev_warn(aspi->dev, "CE%d window invalid", cs);
690 aspeed_spi_chip_enable(aspi, cs, true);
694 dev_dbg(aspi->dev, "CE%d setup done\n", cs);
700 struct aspeed_spi *aspi = spi_controller_get_devdata(spi->controller);
703 aspeed_spi_chip_enable(aspi, cs, false);
705 dev_dbg(aspi->dev, "CE%d cleanup done\n", cs);
708 static void aspeed_spi_enable(struct aspeed_spi *aspi, bool enable)
712 for (cs = 0; cs < aspi->data->max_cs; cs++)
713 aspeed_spi_chip_enable(aspi, cs, enable);
721 struct aspeed_spi *aspi;
729 ctlr = devm_spi_alloc_host(dev, sizeof(*aspi));
733 aspi = spi_controller_get_devdata(ctlr);
734 platform_set_drvdata(pdev, aspi);
735 aspi->data = data;
736 aspi->dev = dev;
738 aspi->regs = devm_platform_ioremap_resource(pdev, 0);
739 if (IS_ERR(aspi->regs))
740 return PTR_ERR(aspi->regs);
742 aspi->ahb_base = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
743 if (IS_ERR(aspi->ahb_base)) {
745 return PTR_ERR(aspi->ahb_base);
748 aspi->ahb_window_size = resource_size(res);
749 aspi->ahb_base_phy = res->start;
751 aspi->clk = devm_clk_get(&pdev->dev, NULL);
752 if (IS_ERR(aspi->clk)) {
754 return PTR_ERR(aspi->clk);
757 aspi->clk_freq = clk_get_rate(aspi->clk);
758 if (!aspi->clk_freq) {
763 ret = clk_prepare_enable(aspi->clk);
787 clk_disable_unprepare(aspi->clk);
793 struct aspeed_spi *aspi = platform_get_drvdata(pdev);
795 aspeed_spi_enable(aspi, false);
796 clk_disable_unprepare(aspi->clk);
808 static u32 aspeed_spi_segment_start(struct aspeed_spi *aspi, u32 reg)
813 static u32 aspeed_spi_segment_end(struct aspeed_spi *aspi, u32 reg)
818 static u32 aspeed_spi_segment_reg(struct aspeed_spi *aspi, u32 start, u32 end)
830 static u32 aspeed_spi_segment_ast2600_start(struct aspeed_spi *aspi,
835 return aspi->ahb_base_phy + start_offset;
838 static u32 aspeed_spi_segment_ast2600_end(struct aspeed_spi *aspi,
845 return aspi->ahb_base_phy;
847 return aspi->ahb_base_phy + end_offset + 0x100000;
850 static u32 aspeed_spi_segment_ast2600_reg(struct aspeed_spi *aspi,
893 struct aspeed_spi *aspi = chip->aspi;
894 const struct aspeed_spi_data *data = aspi->data;
910 writel(fread_timing_val, aspi->regs + data->timing);
913 dev_dbg(aspi->dev,
936 writel(fread_timing_val, aspi->regs + data->timing);
938 dev_dbg(aspi->dev, " * -> good is pass %d [0x%08x]",
974 struct aspeed_spi *aspi = chip->aspi;
975 const struct aspeed_spi_data *data = aspi->data;
976 u32 ahb_freq = aspi->clk_freq;
983 dev_dbg(aspi->dev, "calculate timing compensation - AHB freq: %d MHz",
1001 dev_info(aspi->dev, "Calibration area too uniform, using low speed");
1021 dev_dbg(aspi->dev, "Trying HCLK/%d [%08x] ...", i, tv);
1029 dev_warn(aspi->dev, "No good frequency, using dumb slow");
1031 dev_dbg(aspi->dev, "Found good read timings at HCLK/%d", best_div);
1048 ((chip)->aspi->regs + (chip)->aspi->data->timing + \
1054 struct aspeed_spi *aspi = chip->aspi;
1070 dev_dbg(aspi->dev,
1086 dev_dbg(aspi->dev,