Lines Matching defs:timing
50 /* CEx Read timing compensation register */
78 u32 timing;
862 * Read timing compensation sequences
888 * The timing register is shared by all devices. Only update for CE0.
910 writel(fread_timing_val, aspi->regs + data->timing);
936 writel(fread_timing_val, aspi->regs + data->timing);
983 dev_dbg(aspi->dev, "calculate timing compensation - AHB freq: %d MHz",
1018 /* Set the timing */
1048 ((chip)->aspi->regs + (chip)->aspi->data->timing + \
1093 * value in the read timing register.
1112 .timing = CE0_TIMING_COMPENSATION_REG,
1126 .timing = 0x14,
1138 .timing = CE0_TIMING_COMPENSATION_REG,
1152 .timing = CE0_TIMING_COMPENSATION_REG,
1167 .timing = CE0_TIMING_COMPENSATION_REG,
1182 .timing = CE0_TIMING_COMPENSATION_REG,