Lines Matching defs:ctl_val
68 u32 ctl_val[ASPEED_SPI_MAX];
133 u32 ctl = chip->ctl_val[ASPEED_SPI_BASE];
144 u32 ctl = chip->ctl_val[ASPEED_SPI_READ] |
150 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
301 u32 ctl_val;
314 ctl_val = chip->ctl_val[ASPEED_SPI_BASE];
315 ctl_val &= ~CTRL_IO_CMD_MASK;
317 ctl_val |= op->cmd.opcode << CTRL_COMMAND_SHIFT;
327 ctl_val |= CTRL_IO_ADDRESS_4B;
331 ctl_val |= CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth);
334 ctl_val |= aspeed_spi_get_io_mode(op);
337 ctl_val |= CTRL_IO_MODE_WRITE;
339 ctl_val |= CTRL_IO_MODE_READ;
343 writel(ctl_val, chip->ctl);
361 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
559 u32 ctl_val;
583 ctl_val = readl(chip->ctl) & ~CTRL_IO_CMD_MASK;
584 ctl_val |= aspeed_spi_get_io_mode(op) |
589 ctl_val |= CTRL_IO_DUMMY_SET(op->dummy.nbytes / op->dummy.buswidth);
605 ctl_val |= CTRL_IO_ADDRESS_4B;
609 chip->ctl_val[ASPEED_SPI_READ] = ctl_val;
610 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);
615 chip->cs, op->data.buswidth, chip->ctl_val[ASPEED_SPI_READ]);
692 chip->ctl_val[ASPEED_SPI_BASE] = CTRL_CE_STOP_ACTIVE | CTRL_IO_MODE_USER;
978 u32 ctl_val;
990 ctl_val = chip->ctl_val[ASPEED_SPI_READ] & data->hclk_mask;
991 writel(ctl_val, chip->ctl);
1019 tv = chip->ctl_val[ASPEED_SPI_READ] | ASPEED_SPI_HCLK_DIV(i);
1035 chip->ctl_val[i] = (chip->ctl_val[i] & data->hclk_mask) |
1040 writel(chip->ctl_val[ASPEED_SPI_READ], chip->ctl);