Lines Matching refs:a3700_spi
101 struct a3700_spi {
116 static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset)
118 return readl(a3700_spi->base + offset);
121 static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data)
123 writel(data, a3700_spi->base + offset);
126 static void a3700_spi_auto_cs_unset(struct a3700_spi *a3700_spi)
130 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
132 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
135 static void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs)
139 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
141 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
144 static void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi,
149 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
151 spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
154 static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi,
159 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
176 dev_err(&a3700_spi->host->dev, "wrong pin mode %u", pin_mode);
180 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
185 static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi, bool enable)
189 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
194 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
197 static void a3700_spi_mode_set(struct a3700_spi *a3700_spi,
202 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
214 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
217 static void a3700_spi_clock_set(struct a3700_spi *a3700_spi,
223 prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz);
232 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
236 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
239 val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG);
241 spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val);
245 static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len)
249 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
254 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
256 a3700_spi->byte_len = len;
259 static int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi)
264 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
266 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
269 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
278 static void a3700_spi_init(struct a3700_spi *a3700_spi)
280 struct spi_controller *host = a3700_spi->host;
285 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
287 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
291 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
293 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
296 a3700_spi_auto_cs_unset(a3700_spi);
298 a3700_spi_deactivate_cs(a3700_spi, i);
301 a3700_spi_fifo_mode_set(a3700_spi, true);
304 a3700_spi_mode_set(a3700_spi, host->mode_bits);
307 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);
308 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0);
311 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
312 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U);
318 struct a3700_spi *a3700_spi;
321 a3700_spi = spi_controller_get_devdata(host);
324 cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG);
326 if (!cause || !(a3700_spi->wait_mask & cause))
330 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
331 spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause);
334 complete(&a3700_spi->done);
341 struct a3700_spi *a3700_spi;
346 a3700_spi = spi_controller_get_devdata(spi->controller);
354 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
355 if (a3700_spi->wait_mask & ctrl_reg)
358 reinit_completion(&a3700_spi->done);
360 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG,
361 a3700_spi->wait_mask);
364 timeout = wait_for_completion_timeout(&a3700_spi->done,
367 a3700_spi->wait_mask = 0;
380 ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
381 if (a3700_spi->wait_mask & ctrl_reg)
384 spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
393 struct a3700_spi *a3700_spi;
395 a3700_spi = spi_controller_get_devdata(spi->controller);
396 a3700_spi->wait_mask = bit_mask;
401 static void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi,
406 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
411 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
417 struct a3700_spi *a3700_spi;
419 a3700_spi = spi_controller_get_devdata(spi->controller);
421 a3700_spi_clock_set(a3700_spi, xfer->speed_hz);
426 a3700_spi_bytelen_set(a3700_spi, 4);
429 a3700_spi->tx_buf = xfer->tx_buf;
430 a3700_spi->rx_buf = xfer->rx_buf;
431 a3700_spi->buf_len = xfer->len;
436 struct a3700_spi *a3700_spi = spi_controller_get_devdata(spi->controller);
439 a3700_spi_activate_cs(a3700_spi, spi_get_chipselect(spi, 0));
441 a3700_spi_deactivate_cs(a3700_spi, spi_get_chipselect(spi, 0));
444 static void a3700_spi_header_set(struct a3700_spi *a3700_spi)
450 spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0);
451 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0);
452 spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0);
453 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);
456 if (a3700_spi->tx_buf) {
465 addr_cnt = a3700_spi->buf_len % 4;
469 spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val);
472 a3700_spi->buf_len -= addr_cnt;
477 val = (val << 8) | a3700_spi->tx_buf[0];
478 a3700_spi->tx_buf++;
480 spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val);
485 static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi)
489 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
493 static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi)
497 while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) {
498 val = *(u32 *)a3700_spi->tx_buf;
499 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, cpu_to_le32(val));
500 a3700_spi->buf_len -= 4;
501 a3700_spi->tx_buf += 4;
507 static int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi)
509 u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
514 static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi)
518 while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) {
519 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
520 if (a3700_spi->buf_len >= 4) {
522 memcpy(a3700_spi->rx_buf, &val, 4);
524 a3700_spi->buf_len -= 4;
525 a3700_spi->rx_buf += 4;
532 while (a3700_spi->buf_len) {
533 *a3700_spi->rx_buf = val & 0xff;
536 a3700_spi->buf_len--;
537 a3700_spi->rx_buf++;
545 static void a3700_spi_transfer_abort_fifo(struct a3700_spi *a3700_spi)
550 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
552 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
555 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
561 a3700_spi_fifo_flush(a3700_spi);
564 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
570 struct a3700_spi *a3700_spi = spi_controller_get_devdata(host);
574 ret = clk_enable(a3700_spi->clk);
581 ret = a3700_spi_fifo_flush(a3700_spi);
585 a3700_spi_mode_set(a3700_spi, spi->mode);
594 struct a3700_spi *a3700_spi = spi_controller_get_devdata(host);
600 a3700_spi_fifo_mode_set(a3700_spi, true);
604 a3700_spi_fifo_thres_set(a3700_spi, byte_len);
611 a3700_spi_pin_mode_set(a3700_spi, nbits, xfer->rx_buf ? true : false);
614 a3700_spi_fifo_flush(a3700_spi);
617 a3700_spi_header_set(a3700_spi);
623 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, 0);
626 spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG,
627 a3700_spi->buf_len);
629 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
632 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
635 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
637 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
645 a3700_spi->xmit_data = (a3700_spi->buf_len != 0);
648 while (a3700_spi->buf_len) {
649 if (a3700_spi->tx_buf) {
659 ret = a3700_spi_fifo_write(a3700_spi);
662 } else if (a3700_spi->rx_buf) {
672 ret = a3700_spi_fifo_read(a3700_spi);
690 if (a3700_spi->tx_buf) {
691 if (a3700_spi->xmit_data) {
709 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
711 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
715 val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
728 spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
732 a3700_spi_transfer_abort_fifo(a3700_spi);
743 struct a3700_spi *a3700_spi = spi_controller_get_devdata(host);
747 a3700_spi_fifo_mode_set(a3700_spi, false);
749 while (a3700_spi->buf_len) {
754 if (a3700_spi->buf_len < 4)
755 a3700_spi_bytelen_set(a3700_spi, 1);
757 if (a3700_spi->byte_len == 1)
758 val = *a3700_spi->tx_buf;
760 val = *(u32 *)a3700_spi->tx_buf;
762 spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);
765 while (!(spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG) &
769 val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
771 memcpy(a3700_spi->rx_buf, &val, a3700_spi->byte_len);
773 a3700_spi->buf_len -= a3700_spi->byte_len;
774 a3700_spi->tx_buf += a3700_spi->byte_len;
775 a3700_spi->rx_buf += a3700_spi->byte_len;
799 struct a3700_spi *a3700_spi = spi_controller_get_devdata(host);
801 clk_disable(a3700_spi->clk);
818 struct a3700_spi *spi;
913 struct a3700_spi *spi = spi_controller_get_devdata(host);