Lines Matching refs:ctrl
208 int (*reg_read)(struct qcom_swrm_ctrl *ctrl, int reg, u32 *val);
209 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
280 static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
283 struct regmap *wcd_regmap = ctrl->regmap;
300 static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl *ctrl,
303 struct regmap *wcd_regmap = ctrl->regmap;
320 static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
323 *val = readl(ctrl->mmio + reg);
327 static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
330 writel(val, ctrl->mmio + reg);
352 static int swrm_wait_for_rd_fifo_avail(struct qcom_swrm_ctrl *ctrl)
359 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
371 dev_err_ratelimited(ctrl->dev, "%s err read underflow\n", __func__);
378 static int swrm_wait_for_wr_fifo_avail(struct qcom_swrm_ctrl *ctrl)
385 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
390 if (fifo_outstanding_cmds < ctrl->wr_fifo_depth)
396 if (fifo_outstanding_cmds == ctrl->wr_fifo_depth) {
397 dev_err_ratelimited(ctrl->dev, "%s err write overflow\n", __func__);
404 static bool swrm_wait_for_wr_fifo_done(struct qcom_swrm_ctrl *ctrl)
410 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);
416 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS], &value);
430 static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data,
443 val = swrm_get_packed_reg_val(&ctrl->wcmd_id, cmd_data,
447 if (swrm_wait_for_wr_fifo_avail(ctrl))
451 reinit_completion(&ctrl->broadcast);
454 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val);
456 if (ctrl->version <= SWRM_VERSION_1_3_0)
460 swrm_wait_for_wr_fifo_done(ctrl);
465 ret = wait_for_completion_timeout(&ctrl->broadcast,
478 static int qcom_swrm_cmd_fifo_rd_cmd(struct qcom_swrm_ctrl *ctrl,
484 val = swrm_get_packed_reg_val(&ctrl->rcmd_id, len, dev_addr, reg_addr);
490 swrm_wait_for_wr_fifo_avail(ctrl);
494 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val);
498 if (swrm_wait_for_rd_fifo_avail(ctrl))
502 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_FIFO_ADDR],
507 if (cmd_id != ctrl->rcmd_id) {
511 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD,
513 ctrl->reg_write(ctrl,
514 ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD],
524 dev_err(ctrl->dev, "failed to read fifo: reg: 0x%x, rcmd_id: 0x%x,\
526 reg_addr, ctrl->rcmd_id, dev_addr, cmd_data);
531 static int qcom_swrm_get_alert_slave_dev_num(struct qcom_swrm_ctrl *ctrl)
536 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
542 ctrl->status[dev_num] = status & SWRM_MCP_SLV_STATUS_MASK;
550 static void qcom_swrm_get_device_status(struct qcom_swrm_ctrl *ctrl)
555 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &val);
556 ctrl->slave_status = val;
563 ctrl->status[i] = s;
570 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
573 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &status);
588 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
599 if (!ctrl->status[i])
603 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_1(i), &val1);
606 ctrl->reg_read(ctrl, SWRM_ENUMERATOR_SLAVE_DEV_ID_2(i), &val2);
617 ctrl->clock_stop_not_supported = false;
623 ctrl->clock_stop_not_supported = true;
636 complete(&ctrl->enumeration);
642 struct qcom_swrm_ctrl *ctrl = dev_id;
645 ret = pm_runtime_get_sync(ctrl->dev);
647 dev_err_ratelimited(ctrl->dev,
650 pm_runtime_put_noidle(ctrl->dev);
654 if (ctrl->wake_irq > 0) {
655 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
656 disable_irq_nosync(ctrl->wake_irq);
659 pm_runtime_mark_last_busy(ctrl->dev);
660 pm_runtime_put_autosuspend(ctrl->dev);
667 struct qcom_swrm_ctrl *ctrl = dev_id;
672 clk_prepare_enable(ctrl->hclk);
674 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],
676 intr_sts_masked = intr_sts & ctrl->intr_mask;
686 devnum = qcom_swrm_get_alert_slave_dev_num(ctrl);
688 dev_err_ratelimited(ctrl->dev,
691 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
697 dev_dbg_ratelimited(ctrl->dev, "SWR new slave attached\n");
698 ctrl->reg_read(ctrl, SWRM_MCP_SLV_STATUS, &slave_status);
699 if (ctrl->slave_status == slave_status) {
700 dev_dbg(ctrl->dev, "Slave status not changed %x\n",
703 qcom_swrm_get_device_status(ctrl);
704 qcom_swrm_enumerate(&ctrl->bus);
705 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
709 dev_err_ratelimited(ctrl->dev,
712 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
713 ctrl->reg_write(ctrl,
714 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
715 ctrl->intr_mask);
718 ctrl->reg_read(ctrl,
719 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
721 dev_err_ratelimited(ctrl->dev,
726 ctrl->reg_read(ctrl,
727 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
729 dev_err_ratelimited(ctrl->dev,
734 ctrl->reg_read(ctrl,
735 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
737 dev_err(ctrl->dev,
740 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
743 ctrl->reg_read(ctrl,
744 ctrl->reg_layout[SWRM_REG_CMD_FIFO_STATUS],
746 dev_err_ratelimited(ctrl->dev,
749 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
752 dev_err_ratelimited(ctrl->dev,
755 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
756 ctrl->reg_write(ctrl,
757 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
758 ctrl->intr_mask);
761 dev_err_ratelimited(ctrl->dev,
764 ctrl->intr_mask &=
766 ctrl->reg_write(ctrl,
767 ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
768 ctrl->intr_mask);
771 complete(&ctrl->broadcast);
780 dev_err_ratelimited(ctrl->dev,
787 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
789 ctrl->reg_read(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_STATUS],
791 intr_sts_masked = intr_sts & ctrl->intr_mask;
794 clk_disable_unprepare(ctrl->hclk);
798 static bool swrm_wait_for_frame_gen_enabled(struct qcom_swrm_ctrl *ctrl)
804 ctrl->reg_read(ctrl, SWRM_COMP_STATUS, &comp_sts);
812 dev_err(ctrl->dev, "%s: link status not %s\n", __func__,
818 static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
823 val = FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK, ctrl->rows_index);
824 val |= FIELD_PREP(SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK, ctrl->cols_index);
826 reset_control_reset(ctrl->audio_cgcr);
828 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
831 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
833 ctrl->intr_mask = SWRM_INTERRUPT_STATUS_RMSK;
835 if (ctrl->version < SWRM_VERSION_2_0_0)
836 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
840 ctrl->reg_read(ctrl, SWRM_MCP_CFG_ADDR, &val);
842 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
844 if (ctrl->version == SWRM_VERSION_1_7_0) {
845 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
846 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
848 } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
849 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
850 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
853 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
857 if (ctrl->version >= SWRM_VERSION_1_5_1) {
858 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
862 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
867 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, SWRM_COMP_CFG_ENABLE_MSK);
870 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
873 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
877 if (ctrl->mmio) {
878 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
883 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
887 swrm_wait_for_frame_gen_enabled(ctrl);
888 ctrl->slave_status = 0;
889 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
890 ctrl->rd_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_RD_FIFO_DEPTH, val);
891 ctrl->wr_fifo_depth = FIELD_GET(SWRM_COMP_PARAMS_WR_FIFO_DEPTH, val);
899 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
909 ret = qcom_swrm_cmd_fifo_rd_cmd(ctrl, msg->dev_num,
919 ret = qcom_swrm_cmd_fifo_wr_cmd(ctrl, msg->buf[i],
933 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
936 ctrl->reg_read(ctrl, reg, &val);
938 u32p_replace_bits(&val, ctrl->cols_index, SWRM_MCP_FRAME_CTRL_BANK_COL_CTRL_BMSK);
939 u32p_replace_bits(&val, ctrl->rows_index, SWRM_MCP_FRAME_CTRL_BANK_ROW_CTRL_BMSK);
941 return ctrl->reg_write(ctrl, reg, val);
948 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
950 return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
959 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
965 pcfg = &ctrl->pconfig[params->port_num];
971 ret = ctrl->reg_write(ctrl, reg, value);
978 ret = ctrl->reg_write(ctrl, reg, value);
986 ret = ctrl->reg_write(ctrl, reg, value);
994 ret = ctrl->reg_write(ctrl, reg, value);
1003 ret = ctrl->reg_write(ctrl, reg, value);
1007 ret = ctrl->reg_write(ctrl, reg, value);
1015 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
1027 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1030 ctrl->reg_read(ctrl, reg, &val);
1037 return ctrl->reg_write(ctrl, reg, val);
1053 struct qcom_swrm_ctrl *ctrl = to_qcom_sdw(bus);
1064 pcfg = &ctrl->pconfig[p_rt->num];
1081 pcfg = &ctrl->pconfig[m_port];
1083 pcfg = &ctrl->pconfig[i];
1114 static void qcom_swrm_stream_free_ports(struct qcom_swrm_ctrl *ctrl,
1121 mutex_lock(&ctrl->port_lock);
1125 port_mask = &ctrl->dout_port_mask;
1127 port_mask = &ctrl->din_port_mask;
1133 mutex_unlock(&ctrl->port_lock);
1136 static int qcom_swrm_stream_alloc_ports(struct qcom_swrm_ctrl *ctrl,
1151 mutex_lock(&ctrl->port_lock);
1154 maxport = ctrl->num_dout_ports;
1155 port_mask = &ctrl->dout_port_mask;
1157 maxport = ctrl->num_din_ports;
1158 port_mask = &ctrl->din_port_mask;
1172 dev_err(ctrl->dev, "All ports busy\n");
1194 sdw_stream_add_master(&ctrl->bus, &sconfig, pconfig,
1202 mutex_unlock(&ctrl->port_lock);
1211 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1212 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1215 ret = qcom_swrm_stream_alloc_ports(ctrl, sruntime, params,
1218 qcom_swrm_stream_free_ports(ctrl, sruntime);
1226 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1227 struct sdw_stream_runtime *sruntime = ctrl->sruntime[dai->id];
1229 qcom_swrm_stream_free_ports(ctrl, sruntime);
1230 sdw_stream_remove_master(&ctrl->bus, sruntime);
1238 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1240 ctrl->sruntime[dai->id] = stream;
1247 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1249 return ctrl->sruntime[dai->id];
1255 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1261 ret = pm_runtime_get_sync(ctrl->dev);
1263 dev_err_ratelimited(ctrl->dev,
1266 pm_runtime_put_noidle(ctrl->dev);
1276 ctrl->sruntime[dai->id] = sruntime;
1293 pm_runtime_mark_last_busy(ctrl->dev);
1294 pm_runtime_put_autosuspend(ctrl->dev);
1302 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
1304 swrm_wait_for_wr_fifo_done(ctrl);
1305 sdw_release_stream(ctrl->sruntime[dai->id]);
1306 ctrl->sruntime[dai->id] = NULL;
1307 pm_runtime_mark_last_busy(ctrl->dev);
1308 pm_runtime_put_autosuspend(ctrl->dev);
1325 static int qcom_swrm_register_dais(struct qcom_swrm_ctrl *ctrl)
1327 int num_dais = ctrl->num_dout_ports + ctrl->num_din_ports;
1330 struct device *dev = ctrl->dev;
1343 if (i < ctrl->num_dout_ports)
1357 return devm_snd_soc_register_component(ctrl->dev,
1362 static int qcom_swrm_get_port_config(struct qcom_swrm_ctrl *ctrl)
1364 struct device_node *np = ctrl->dev->of_node;
1377 ctrl->reg_read(ctrl, SWRM_COMP_PARAMS, &val);
1379 ctrl->num_dout_ports = FIELD_GET(SWRM_COMP_PARAMS_DOUT_PORTS_MASK, val);
1380 ctrl->num_din_ports = FIELD_GET(SWRM_COMP_PARAMS_DIN_PORTS_MASK, val);
1386 if (val > ctrl->num_din_ports)
1389 ctrl->num_din_ports = val;
1395 if (val > ctrl->num_dout_ports)
1398 ctrl->num_dout_ports = val;
1400 nports = ctrl->num_dout_ports + ctrl->num_din_ports;
1405 set_bit(0, &ctrl->dout_port_mask);
1406 set_bit(0, &ctrl->din_port_mask);
1431 if (ctrl->version <= SWRM_VERSION_1_3_0)
1455 ctrl->pconfig[i + 1].si = si[i];
1457 ctrl->pconfig[i + 1].si = ((u8 *)si)[i];
1458 ctrl->pconfig[i + 1].off1 = off1[i];
1459 ctrl->pconfig[i + 1].off2 = off2[i];
1460 ctrl->pconfig[i + 1].bp_mode = bp_mode[i];
1461 ctrl->pconfig[i + 1].hstart = hstart[i];
1462 ctrl->pconfig[i + 1].hstop = hstop[i];
1463 ctrl->pconfig[i + 1].word_length = word_length[i];
1464 ctrl->pconfig[i + 1].blk_group_count = blk_group_count[i];
1465 ctrl->pconfig[i + 1].lane_control = lane_control[i];
1474 struct qcom_swrm_ctrl *ctrl = s_file->private;
1477 ret = pm_runtime_get_sync(ctrl->dev);
1479 dev_err_ratelimited(ctrl->dev,
1482 pm_runtime_put_noidle(ctrl->dev);
1486 for (reg = 0; reg <= ctrl->max_reg; reg += 4) {
1487 ctrl->reg_read(ctrl, reg, ®_val);
1490 pm_runtime_mark_last_busy(ctrl->dev);
1491 pm_runtime_put_autosuspend(ctrl->dev);
1504 struct qcom_swrm_ctrl *ctrl;
1509 ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
1510 if (!ctrl)
1514 ctrl->max_reg = data->max_reg;
1515 ctrl->reg_layout = data->reg_layout;
1516 ctrl->rows_index = sdw_find_row_index(data->default_rows);
1517 ctrl->cols_index = sdw_find_col_index(data->default_cols);
1523 ctrl->reg_read = qcom_swrm_ahb_reg_read;
1524 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1525 ctrl->regmap = dev_get_regmap(dev->parent, NULL);
1526 if (!ctrl->regmap)
1529 ctrl->reg_read = qcom_swrm_cpu_reg_read;
1530 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1531 ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
1532 if (IS_ERR(ctrl->mmio))
1533 return PTR_ERR(ctrl->mmio);
1537 ctrl->audio_cgcr = devm_reset_control_get_optional_exclusive(dev, "swr_audio_cgcr");
1538 if (IS_ERR(ctrl->audio_cgcr)) {
1539 dev_err(dev, "Failed to get cgcr reset ctrl required for SW gating\n");
1540 ret = PTR_ERR(ctrl->audio_cgcr);
1545 ctrl->irq = of_irq_get(dev->of_node, 0);
1546 if (ctrl->irq < 0) {
1547 ret = ctrl->irq;
1551 ctrl->hclk = devm_clk_get(dev, "iface");
1552 if (IS_ERR(ctrl->hclk)) {
1553 ret = PTR_ERR(ctrl->hclk);
1557 clk_prepare_enable(ctrl->hclk);
1559 ctrl->dev = dev;
1560 dev_set_drvdata(&pdev->dev, ctrl);
1561 mutex_init(&ctrl->port_lock);
1562 init_completion(&ctrl->broadcast);
1563 init_completion(&ctrl->enumeration);
1565 ctrl->bus.ops = &qcom_swrm_ops;
1566 ctrl->bus.port_ops = &qcom_swrm_port_ops;
1567 ctrl->bus.compute_params = &qcom_swrm_compute_params;
1568 ctrl->bus.clk_stop_timeout = 300;
1570 ret = qcom_swrm_get_port_config(ctrl);
1574 params = &ctrl->bus.params;
1579 ctrl->reg_read(ctrl, SWRM_MCP_STATUS, &val);
1583 prop = &ctrl->bus.prop;
1591 ctrl->reg_read(ctrl, SWRM_COMP_HW_VERSION, &ctrl->version);
1593 ret = devm_request_threaded_irq(dev, ctrl->irq, NULL,
1597 "soundwire", ctrl);
1603 ctrl->wake_irq = of_irq_get(dev->of_node, 1);
1604 if (ctrl->wake_irq > 0) {
1605 ret = devm_request_threaded_irq(dev, ctrl->wake_irq, NULL,
1608 "swr_wake_irq", ctrl);
1616 ctrl->bus.controller_id = -1;
1618 ret = sdw_bus_master_add(&ctrl->bus, dev, dev->fwnode);
1625 qcom_swrm_init(ctrl);
1626 wait_for_completion_timeout(&ctrl->enumeration,
1628 ret = qcom_swrm_register_dais(ctrl);
1633 (ctrl->version >> 24) & 0xff, (ctrl->version >> 16) & 0xff,
1634 ctrl->version & 0xffff);
1643 ctrl->debugfs = debugfs_create_dir("qualcomm-sdw", ctrl->bus.debugfs);
1644 debugfs_create_file("qualcomm-registers", 0400, ctrl->debugfs, ctrl,
1651 sdw_bus_master_delete(&ctrl->bus);
1653 clk_disable_unprepare(ctrl->hclk);
1660 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(&pdev->dev);
1662 sdw_bus_master_delete(&ctrl->bus);
1663 clk_disable_unprepare(ctrl->hclk);
1670 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1673 if (ctrl->wake_irq > 0) {
1674 if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1675 disable_irq_nosync(ctrl->wake_irq);
1678 clk_prepare_enable(ctrl->hclk);
1680 if (ctrl->clock_stop_not_supported) {
1681 reinit_completion(&ctrl->enumeration);
1682 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1685 qcom_swrm_init(ctrl);
1688 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1689 dev_err(ctrl->dev, "link failed to connect\n");
1692 wait_for_completion_timeout(&ctrl->enumeration,
1694 qcom_swrm_get_device_status(ctrl);
1695 sdw_handle_slave_status(&ctrl->bus, ctrl->status);
1697 reset_control_reset(ctrl->audio_cgcr);
1699 if (ctrl->version == SWRM_VERSION_1_7_0) {
1700 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1701 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
1703 } else if (ctrl->version >= SWRM_VERSION_2_0_0) {
1704 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1705 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
1708 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1710 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
1713 ctrl->intr_mask |= SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1714 if (ctrl->version < SWRM_VERSION_2_0_0)
1715 ctrl->reg_write(ctrl,
1716 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1717 ctrl->intr_mask);
1718 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1719 ctrl->intr_mask);
1722 if (!swrm_wait_for_frame_gen_enabled(ctrl))
1723 dev_err(ctrl->dev, "link failed to connect\n");
1725 ret = sdw_bus_exit_clk_stop(&ctrl->bus);
1727 dev_err(ctrl->dev, "bus failed to exit clock stop %d\n", ret);
1735 struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev);
1738 swrm_wait_for_wr_fifo_done(ctrl);
1739 if (!ctrl->clock_stop_not_supported) {
1741 ctrl->intr_mask &= ~SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET;
1742 if (ctrl->version < SWRM_VERSION_2_0_0)
1743 ctrl->reg_write(ctrl,
1744 ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
1745 ctrl->intr_mask);
1746 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1747 ctrl->intr_mask);
1749 ret = sdw_bus_prep_clk_stop(&ctrl->bus);
1755 ret = sdw_bus_clk_stop(&ctrl->bus);
1762 clk_disable_unprepare(ctrl->hclk);
1766 if (ctrl->wake_irq > 0) {
1767 if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq)))
1768 enable_irq(ctrl->wake_irq);