Lines Matching defs:reg_write
209 int (*reg_write)(struct qcom_swrm_ctrl *ctrl, int reg, int val);
454 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_WR_CMD], val);
494 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_CMD_FIFO_RD_CMD], val);
511 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD,
513 ctrl->reg_write(ctrl,
713 ctrl->reg_write(ctrl,
740 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
749 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CMD, 0x1);
756 ctrl->reg_write(ctrl,
766 ctrl->reg_write(ctrl,
787 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
828 ctrl->reg_write(ctrl, SWRM_MCP_FRAME_CTRL_BANK_ADDR(0), val);
831 ctrl->reg_write(ctrl, SWRM_ENUMERATOR_CFG_ADDR, 1);
836 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_MASK_ADDR],
842 ctrl->reg_write(ctrl, SWRM_MCP_CFG_ADDR, val);
845 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
846 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
849 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
850 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
853 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
858 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
862 ctrl->reg_write(ctrl, SWRM_CMD_FIFO_CFG_ADDR,
867 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR, SWRM_COMP_CFG_ENABLE_MSK);
870 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
873 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
878 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
883 ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
941 return ctrl->reg_write(ctrl, reg, val);
950 return ctrl->reg_write(ctrl, SWRM_DP_BLOCK_CTRL_1(p_params->num),
971 ret = ctrl->reg_write(ctrl, reg, value);
978 ret = ctrl->reg_write(ctrl, reg, value);
986 ret = ctrl->reg_write(ctrl, reg, value);
994 ret = ctrl->reg_write(ctrl, reg, value);
1003 ret = ctrl->reg_write(ctrl, reg, value);
1007 ret = ctrl->reg_write(ctrl, reg, value);
1015 ret = ctrl->reg_write(ctrl, reg, pcfg->bp_mode);
1037 return ctrl->reg_write(ctrl, reg, val);
1524 ctrl->reg_write = qcom_swrm_ahb_reg_write;
1530 ctrl->reg_write = qcom_swrm_cpu_reg_write;
1682 ctrl->reg_write(ctrl, SWRM_COMP_SW_RESET, 0x01);
1700 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1701 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL,
1704 ctrl->reg_write(ctrl, SWRM_LINK_MANAGER_EE, SWRM_EE_CPU);
1705 ctrl->reg_write(ctrl, SWRM_V2_0_CLK_CTRL,
1708 ctrl->reg_write(ctrl, SWRM_MCP_BUS_CTRL, SWRM_MCP_BUS_CLK_START);
1710 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CLEAR],
1715 ctrl->reg_write(ctrl,
1718 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],
1743 ctrl->reg_write(ctrl,
1746 ctrl->reg_write(ctrl, ctrl->reg_layout[SWRM_REG_INTERRUPT_CPU_EN],