Lines Matching refs:params
397 struct sdw_bus_params *b_params = &bus->params;
403 hstop = bus->params.col - 1;
408 rate = m_rt->stream->params.rate;
409 bps = m_rt->stream->params.bps;
410 sample_int = (bus->params.curr_dr_freq / rate);
461 struct sdw_transport_params *params,
475 frame_fmt_reg = sdw0_manager_dp_reg[params->port_num].frame_fmt_reg;
476 sample_int_reg = sdw0_manager_dp_reg[params->port_num].sample_int_reg;
477 hctrl_dp0_reg = sdw0_manager_dp_reg[params->port_num].hctrl_dp0_reg;
478 offset_reg = sdw0_manager_dp_reg[params->port_num].offset_reg;
479 lane_ctrl_ch_en_reg = sdw0_manager_dp_reg[params->port_num].lane_ctrl_ch_en_reg;
482 frame_fmt_reg = sdw1_manager_dp_reg[params->port_num].frame_fmt_reg;
483 sample_int_reg = sdw1_manager_dp_reg[params->port_num].sample_int_reg;
484 hctrl_dp0_reg = sdw1_manager_dp_reg[params->port_num].hctrl_dp0_reg;
485 offset_reg = sdw1_manager_dp_reg[params->port_num].offset_reg;
486 lane_ctrl_ch_en_reg = sdw1_manager_dp_reg[params->port_num].lane_ctrl_ch_en_reg;
494 u32p_replace_bits(&dpn_frame_fmt, params->blk_pkg_mode, AMD_DPN_FRAME_FMT_BLK_PKG_MODE);
495 u32p_replace_bits(&dpn_frame_fmt, params->blk_grp_ctrl, AMD_DPN_FRAME_FMT_BLK_GRP_CTRL);
499 dpn_sampleinterval = params->sample_interval - 1;
502 dpn_hctrl = FIELD_PREP(AMD_DPN_HCTRL_HSTOP, params->hstop);
503 dpn_hctrl |= FIELD_PREP(AMD_DPN_HCTRL_HSTART, params->hstart);
506 dpn_offsetctrl = FIELD_PREP(AMD_DPN_OFFSET_CTRL_1, params->offset1);
507 dpn_offsetctrl |= FIELD_PREP(AMD_DPN_OFFSET_CTRL_2, params->offset2);
515 u32p_replace_bits(&dpn_lanectrl, params->lane_ctrl, AMD_DPN_CH_EN_LCTRL);
603 struct snd_pcm_hw_params *params,
617 ch = params_channels(params);
626 sconfig.frame_rate = params_rate(params);
629 sconfig.bps = snd_pcm_format_width(params_format(params));
900 struct sdw_bus_params *params;
952 params = &amd_manager->bus.params;
953 params->max_dr_freq = AMD_SDW_DEFAULT_CLK_FREQ * 2;
954 params->curr_dr_freq = AMD_SDW_DEFAULT_CLK_FREQ * 2;
955 params->col = AMD_SDW_DEFAULT_COLUMNS;
956 params->row = AMD_SDW_DEFAULT_ROWS;