Lines Matching refs:pmc
3 * drivers/soc/tegra/pmc.c
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
54 #include <soc/tegra/pmc.h>
61 #include <dt-bindings/soc/tegra-pmc.h>
269 struct tegra_pmc *pmc;
357 void (*init)(struct tegra_pmc *pmc);
358 void (*setup_irq_polarity)(struct tegra_pmc *pmc,
361 void (*set_wake_filters)(struct tegra_pmc *pmc);
364 int (*powergate_set)(struct tegra_pmc *pmc, unsigned int id,
472 static struct tegra_pmc *pmc = &(struct tegra_pmc) {
483 static u32 tegra_pmc_readl(struct tegra_pmc *pmc, unsigned long offset)
487 if (pmc->tz_only) {
491 if (pmc->dev)
492 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
502 return readl(pmc->base + offset);
505 static void tegra_pmc_writel(struct tegra_pmc *pmc, u32 value,
510 if (pmc->tz_only) {
514 if (pmc->dev)
515 dev_warn(pmc->dev, "%s(): SMC failed: %lu\n",
522 writel(value, pmc->base + offset);
526 static u32 tegra_pmc_scratch_readl(struct tegra_pmc *pmc, unsigned long offset)
528 if (pmc->tz_only)
529 return tegra_pmc_readl(pmc, offset);
531 return readl(pmc->scratch + offset);
534 static void tegra_pmc_scratch_writel(struct tegra_pmc *pmc, u32 value,
537 if (pmc->tz_only)
538 tegra_pmc_writel(pmc, value, offset);
540 writel(value, pmc->scratch + offset);
550 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
551 return (tegra_pmc_readl(pmc, GPU_RG_CNTRL) & 0x1) == 0;
553 return (tegra_pmc_readl(pmc, PWRGATE_STATUS) & BIT(id)) != 0;
556 static inline bool tegra_powergate_is_valid(struct tegra_pmc *pmc, int id)
558 return (pmc->soc && pmc->soc->powergates[id]);
561 static inline bool tegra_powergate_is_available(struct tegra_pmc *pmc, int id)
563 return test_bit(id, pmc->powergates_available);
566 static int tegra_powergate_lookup(struct tegra_pmc *pmc, const char *name)
570 if (!pmc || !pmc->soc || !name)
573 for (i = 0; i < pmc->soc->num_powergates; i++) {
574 if (!tegra_powergate_is_valid(pmc, i))
577 if (!strcmp(name, pmc->soc->powergates[i]))
584 static int tegra20_powergate_set(struct tegra_pmc *pmc, unsigned int id,
597 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
607 static inline bool tegra_powergate_toggle_ready(struct tegra_pmc *pmc)
609 return !(tegra_pmc_readl(pmc, PWRGATE_TOGGLE) & PWRGATE_TOGGLE_START);
612 static int tegra114_powergate_set(struct tegra_pmc *pmc, unsigned int id,
619 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
624 tegra_pmc_writel(pmc, PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE);
627 err = readx_poll_timeout(tegra_powergate_toggle_ready, pmc, status,
643 * @pmc: power management controller
647 static int tegra_powergate_set(struct tegra_pmc *pmc, unsigned int id,
652 if (id == TEGRA_POWERGATE_3D && pmc->soc->has_gpu_clamps)
655 mutex_lock(&pmc->powergates_lock);
658 mutex_unlock(&pmc->powergates_lock);
662 err = pmc->soc->powergate_set(pmc, id, new_state);
664 mutex_unlock(&pmc->powergates_lock);
669 static int __tegra_powergate_remove_clamping(struct tegra_pmc *pmc,
674 mutex_lock(&pmc->powergates_lock);
681 if (pmc->soc->has_gpu_clamps) {
682 tegra_pmc_writel(pmc, 0, GPU_RG_CNTRL);
698 tegra_pmc_writel(pmc, mask, REMOVE_CLAMPING);
701 mutex_unlock(&pmc->powergates_lock);
796 err = tegra_powergate_set(pg->pmc, pg->id, true);
812 err = __tegra_powergate_remove_clamping(pg->pmc, pg->id);
824 if (pg->pmc->soc->needs_mbist_war)
846 tegra_powergate_set(pg->pmc, pg->id, false);
875 err = tegra_powergate_set(pg->pmc, pg->id, false);
903 struct device *dev = pg->pmc->dev;
922 struct device *dev = pg->pmc->dev;
948 if (!tegra_powergate_is_available(pmc, id))
951 return tegra_powergate_set(pmc, id, true);
961 if (!tegra_powergate_is_available(pmc, id))
964 return tegra_powergate_set(pmc, id, false);
970 * @pmc: power management controller
973 static int tegra_powergate_is_powered(struct tegra_pmc *pmc, unsigned int id)
975 if (!tegra_powergate_is_valid(pmc, id))
987 if (!tegra_powergate_is_available(pmc, id))
990 return __tegra_powergate_remove_clamping(pmc, id);
1008 if (!tegra_powergate_is_available(pmc, id))
1025 pg->pmc = pmc;
1029 dev_err(pmc->dev, "failed to turn on partition %d: %d\n", id,
1041 * @pmc: power management controller
1047 static int tegra_get_cpu_powergate_id(struct tegra_pmc *pmc,
1050 if (pmc->soc && cpuid < pmc->soc->num_cpu_powergates)
1051 return pmc->soc->cpu_powergates[cpuid];
1064 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1068 return tegra_powergate_is_powered(pmc, id);
1079 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1083 return tegra_powergate_set(pmc, id, true);
1094 id = tegra_get_cpu_powergate_id(pmc, cpuid);
1105 value = tegra_pmc_scratch_readl(pmc, pmc->soc->regs->scratch0);
1119 tegra_pmc_scratch_writel(pmc, value, pmc->soc->regs->scratch0);
1140 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1142 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1162 tegra_pmc_writel(pmc, go_to_charger_mode, PMC_SCRATCH37);
1177 for (i = 0; i < pmc->soc->num_powergates; i++) {
1178 status = tegra_powergate_is_powered(pmc, i);
1182 seq_printf(s, " %9s %7s\n", pmc->soc->powergates[i],
1237 struct device *dev = pg->pmc->dev;
1272 static int tegra_powergate_add(struct tegra_pmc *pmc, struct device_node *np)
1274 struct device *dev = pmc->dev;
1283 id = tegra_powergate_lookup(pmc, np->name);
1294 clear_bit(id, pmc->powergates_available);
1300 pg->pmc = pmc;
1302 off = !tegra_powergate_is_powered(pmc, pg->id);
1354 set_bit(id, pmc->powergates_available);
1364 return pmc->core_domain_state_synced;
1381 mutex_lock(&pmc->powergates_lock);
1382 err = dev_pm_opp_set_opp(pmc->dev, opp);
1383 mutex_unlock(&pmc->powergates_lock);
1403 static int tegra_pmc_core_pd_add(struct tegra_pmc *pmc, struct device_node *np)
1409 genpd = devm_kzalloc(pmc->dev, sizeof(*genpd), GFP_KERNEL);
1417 err = devm_pm_opp_set_regulators(pmc->dev, rname);
1419 return dev_err_probe(pmc->dev, err,
1424 dev_err(pmc->dev, "failed to init core genpd: %d\n", err);
1430 dev_err(pmc->dev, "failed to add core genpd: %d\n", err);
1434 pmc->core_domain_registered = true;
1444 static int tegra_powergate_init(struct tegra_pmc *pmc,
1457 err = tegra_pmc_core_pd_add(pmc, np);
1468 err = tegra_powergate_add(pmc, child);
1506 set_bit(pg->id, pmc->powergates_available);
1540 tegra_io_pad_find(struct tegra_pmc *pmc, enum tegra_io_pad id)
1544 for (i = 0; i < pmc->soc->num_io_pads; i++)
1545 if (pmc->soc->io_pads[i].id == id)
1546 return &pmc->soc->io_pads[i];
1551 static int tegra_io_pad_prepare(struct tegra_pmc *pmc,
1566 if (pmc->clk) {
1567 rate = pmc->rate;
1569 dev_err(pmc->dev, "failed to get clock rate\n");
1573 tegra_pmc_writel(pmc, DPD_SAMPLE_ENABLE, DPD_SAMPLE);
1578 tegra_pmc_writel(pmc, value, SEL_DPD_TIM);
1584 static int tegra_io_pad_poll(struct tegra_pmc *pmc, unsigned long offset,
1592 value = tegra_pmc_readl(pmc, offset);
1602 static void tegra_io_pad_unprepare(struct tegra_pmc *pmc)
1604 if (pmc->clk)
1605 tegra_pmc_writel(pmc, DPD_SAMPLE_DISABLE, DPD_SAMPLE);
1621 pad = tegra_io_pad_find(pmc, id);
1623 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1627 mutex_lock(&pmc->powergates_lock);
1629 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask);
1631 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1635 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_OFF | mask, request);
1637 err = tegra_io_pad_poll(pmc, status, mask, 0, 250);
1639 dev_err(pmc->dev, "failed to enable I/O pad: %d\n", err);
1643 tegra_io_pad_unprepare(pmc);
1646 mutex_unlock(&pmc->powergates_lock);
1664 pad = tegra_io_pad_find(pmc, id);
1666 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1670 mutex_lock(&pmc->powergates_lock);
1672 err = tegra_io_pad_prepare(pmc, pad, &request, &status, &mask);
1674 dev_err(pmc->dev, "failed to prepare I/O pad: %d\n", err);
1678 tegra_pmc_writel(pmc, IO_DPD_REQ_CODE_ON | mask, request);
1680 err = tegra_io_pad_poll(pmc, status, mask, mask, 250);
1682 dev_err(pmc->dev, "failed to disable I/O pad: %d\n", err);
1686 tegra_io_pad_unprepare(pmc);
1689 mutex_unlock(&pmc->powergates_lock);
1694 static int tegra_io_pad_is_powered(struct tegra_pmc *pmc, enum tegra_io_pad id)
1700 pad = tegra_io_pad_find(pmc, id);
1702 dev_err(pmc->dev, "invalid I/O pad ID %u\n", id);
1712 value = tegra_pmc_readl(pmc, status);
1717 static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,
1723 pad = tegra_io_pad_find(pmc, id);
1730 mutex_lock(&pmc->powergates_lock);
1732 if (pmc->soc->has_impl_33v_pwr) {
1733 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1740 tegra_pmc_writel(pmc, value, PMC_IMPL_E_33V_PWR);
1743 value = tegra_pmc_readl(pmc, PMC_PWR_DET);
1745 tegra_pmc_writel(pmc, value, PMC_PWR_DET);
1748 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1755 tegra_pmc_writel(pmc, value, PMC_PWR_DET_VALUE);
1758 mutex_unlock(&pmc->powergates_lock);
1765 static int tegra_io_pad_get_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id)
1770 pad = tegra_io_pad_find(pmc, id);
1777 if (pmc->soc->has_impl_33v_pwr)
1778 value = tegra_pmc_readl(pmc, PMC_IMPL_E_33V_PWR);
1780 value = tegra_pmc_readl(pmc, PMC_PWR_DET_VALUE);
1815 return pmc->suspend_mode;
1823 pmc->suspend_mode = mode;
1838 rate = pmc->rate;
1848 ticks = pmc->cpu_good_time * rate + USEC_PER_SEC - 1;
1850 tegra_pmc_writel(pmc, ticks, PMC_CPUPWRGOOD_TIMER);
1852 ticks = pmc->cpu_off_time * rate + USEC_PER_SEC - 1;
1854 tegra_pmc_writel(pmc, ticks, PMC_CPUPWROFF_TIMER);
1856 value = tegra_pmc_readl(pmc, PMC_CNTRL);
1859 tegra_pmc_writel(pmc, value, PMC_CNTRL);
1863 static int tegra_pmc_parse_dt(struct tegra_pmc *pmc, struct device_node *np)
1868 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1872 pmc->suspend_mode = TEGRA_SUSPEND_LP0;
1876 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1880 pmc->suspend_mode = TEGRA_SUSPEND_LP2;
1884 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1889 pmc->suspend_mode = tegra_pm_validate_suspend_mode(pmc->suspend_mode);
1892 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1894 pmc->cpu_good_time = value;
1897 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1899 pmc->cpu_off_time = value;
1903 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1905 pmc->core_osc_time = values[0];
1906 pmc->core_pmu_time = values[1];
1909 pmc->suspend_mode = TEGRA_SUSPEND_NONE;
1911 pmc->core_off_time = value;
1913 pmc->corereq_high = of_property_read_bool(np,
1916 pmc->sysclkreq_high = of_property_read_bool(np,
1919 pmc->combined_req = of_property_read_bool(np,
1922 pmc->cpu_pwr_good_en = of_property_read_bool(np,
1927 if (pmc->suspend_mode == TEGRA_SUSPEND_LP0)
1928 pmc->suspend_mode = TEGRA_SUSPEND_LP1;
1930 pmc->lp0_vec_phys = values[0];
1931 pmc->lp0_vec_size = values[1];
1936 static int tegra_pmc_init(struct tegra_pmc *pmc)
1938 if (pmc->soc->max_wake_events > 0) {
1939 pmc->wake_type_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
1940 if (!pmc->wake_type_level_map)
1943 pmc->wake_type_dual_edge_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
1944 if (!pmc->wake_type_dual_edge_map)
1947 pmc->wake_sw_status_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
1948 if (!pmc->wake_sw_status_map)
1951 pmc->wake_cntrl_level_map = bitmap_zalloc(pmc->soc->max_wake_events, GFP_KERNEL);
1952 if (!pmc->wake_cntrl_level_map)
1956 if (pmc->soc->init)
1957 pmc->soc->init(pmc);
1962 static void tegra_pmc_init_tsense_reset(struct tegra_pmc *pmc)
1966 struct device *dev = pmc->dev;
1970 if (!pmc->soc->has_tsense_reset)
1973 np = of_get_child_by_name(pmc->dev->of_node, "i2c-thermtrip");
2002 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
2004 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
2008 tegra_pmc_writel(pmc, value, PMC_SCRATCH54);
2026 tegra_pmc_writel(pmc, value, PMC_SCRATCH55);
2028 value = tegra_pmc_readl(pmc, PMC_SENSOR_CTRL);
2030 tegra_pmc_writel(pmc, value, PMC_SENSOR_CTRL);
2032 dev_info(pmc->dev, "emergency thermal reset enabled\n");
2040 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2042 return pmc->soc->num_io_pads;
2048 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl);
2050 return pmc->soc->io_pads[group].name;
2058 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2060 *pins = &pmc->soc->io_pads[group].id;
2078 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2083 pad = tegra_io_pad_find(pmc, pin);
2089 ret = tegra_io_pad_get_voltage(pmc, pad->id);
2097 ret = tegra_io_pad_is_powered(pmc, pad->id);
2117 struct tegra_pmc *pmc = pinctrl_dev_get_drvdata(pctl_dev);
2124 pad = tegra_io_pad_find(pmc, pin);
2145 err = tegra_io_pad_set_voltage(pmc, pad->id, arg);
2168 static int tegra_pmc_pinctrl_init(struct tegra_pmc *pmc)
2172 if (!pmc->soc->num_pin_descs)
2175 tegra_pmc_pctl_desc.name = dev_name(pmc->dev);
2176 tegra_pmc_pctl_desc.pins = pmc->soc->pin_descs;
2177 tegra_pmc_pctl_desc.npins = pmc->soc->num_pin_descs;
2179 pmc->pctl_dev = devm_pinctrl_register(pmc->dev, &tegra_pmc_pctl_desc,
2180 pmc);
2181 if (IS_ERR(pmc->pctl_dev)) {
2182 err = PTR_ERR(pmc->pctl_dev);
2183 dev_err(pmc->dev, "failed to register pin controller: %d\n",
2196 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2197 value &= pmc->soc->regs->rst_source_mask;
2198 value >>= pmc->soc->regs->rst_source_shift;
2200 if (WARN_ON(value >= pmc->soc->num_reset_sources))
2203 return sprintf(buf, "%s\n", pmc->soc->reset_sources[value]);
2213 value = tegra_pmc_readl(pmc, pmc->soc->regs->rst_status);
2214 value &= pmc->soc->regs->rst_level_mask;
2215 value >>= pmc->soc->regs->rst_level_shift;
2217 if (WARN_ON(value >= pmc->soc->num_reset_levels))
2220 return sprintf(buf, "%s\n", pmc->soc->reset_levels[value]);
2225 static void tegra_pmc_reset_sysfs_init(struct tegra_pmc *pmc)
2227 struct device *dev = pmc->dev;
2230 if (pmc->soc->reset_sources) {
2238 if (pmc->soc->reset_levels) {
2264 struct tegra_pmc *pmc = domain->host_data;
2265 const struct tegra_pmc_soc *soc = pmc->soc;
2285 &pmc->irq, pmc);
2295 spec.fwnode = &pmc->dev->of_node->fwnode;
2315 &pmc->irq, pmc);
2339 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2347 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE_STATUS);
2348 tegra_pmc_writel(pmc, 0, PMC_SW_WAKE2_STATUS);
2350 tegra_pmc_writel(pmc, 0, PMC_WAKE_STATUS);
2351 tegra_pmc_writel(pmc, 0, PMC_WAKE2_STATUS);
2359 value = tegra_pmc_readl(pmc, offset);
2366 tegra_pmc_writel(pmc, value, offset);
2373 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2385 value = tegra_pmc_readl(pmc, offset);
2406 tegra_pmc_writel(pmc, value, offset);
2411 static void tegra186_pmc_set_wake_filters(struct tegra_pmc *pmc)
2416 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID));
2418 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(SW_WAKE_ID));
2419 dev_dbg(pmc->dev, "WAKE_AOWAKE_CNTRL_83 = 0x%x\n", value);
2424 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2432 writel(0x1, pmc->wake + WAKE_AOWAKE_STATUS_W(data->hwirq));
2435 value = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2442 writel(value, pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(offset));
2445 writel(!!on, pmc->wake + WAKE_AOWAKE_MASK_W(data->hwirq));
2452 struct tegra_pmc *pmc = irq_data_get_irq_chip_data(data);
2455 value = readl(pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2461 set_bit(data->hwirq, pmc->wake_type_level_map);
2462 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map);
2468 clear_bit(data->hwirq, pmc->wake_type_level_map);
2469 clear_bit(data->hwirq, pmc->wake_type_dual_edge_map);
2474 clear_bit(data->hwirq, pmc->wake_type_level_map);
2475 set_bit(data->hwirq, pmc->wake_type_dual_edge_map);
2482 writel(value, pmc->wake + WAKE_AOWAKE_CNTRL(data->hwirq));
2515 static int tegra_pmc_irq_init(struct tegra_pmc *pmc)
2520 np = of_irq_find_parent(pmc->dev->of_node);
2529 pmc->irq.name = dev_name(pmc->dev);
2530 pmc->irq.irq_mask = tegra_irq_mask_parent;
2531 pmc->irq.irq_unmask = tegra_irq_unmask_parent;
2532 pmc->irq.irq_eoi = tegra_irq_eoi_parent;
2533 pmc->irq.irq_set_affinity = tegra_irq_set_affinity_parent;
2534 pmc->irq.irq_set_type = pmc->soc->irq_set_type;
2535 pmc->irq.irq_set_wake = pmc->soc->irq_set_wake;
2537 pmc->domain = irq_domain_add_hierarchy(parent, 0, 96, pmc->dev->of_node,
2538 &tegra_pmc_irq_domain_ops, pmc);
2539 if (!pmc->domain) {
2540 dev_err(pmc->dev, "failed to allocate domain\n");
2550 struct tegra_pmc *pmc = container_of(nb, struct tegra_pmc, clk_nb);
2555 mutex_lock(&pmc->powergates_lock);
2559 pmc->rate = data->new_rate;
2563 mutex_unlock(&pmc->powergates_lock);
2576 tegra_pmc_readl(pmc, offset);
2577 /* pmc clk propagation delay 2 us */
2586 val = tegra_pmc_readl(pmc, clk->offs) >> clk->mux_shift;
2597 val = tegra_pmc_readl(pmc, clk->offs);
2600 tegra_pmc_writel(pmc, val, clk->offs);
2611 val = tegra_pmc_readl(pmc, clk->offs) & BIT(clk->force_en_shift);
2620 val = tegra_pmc_readl(pmc, offs);
2622 tegra_pmc_writel(pmc, val, offs);
2652 tegra_pmc_clk_out_register(struct tegra_pmc *pmc,
2659 pmc_clk = devm_kzalloc(pmc->dev, sizeof(*pmc_clk), GFP_KERNEL);
2682 return tegra_pmc_readl(pmc, gate->offs) & BIT(gate->shift) ? 1 : 0;
2708 tegra_pmc_clk_gate_register(struct tegra_pmc *pmc, const char *name,
2715 gate = devm_kzalloc(pmc->dev, sizeof(*gate), GFP_KERNEL);
2732 static void tegra_pmc_clock_register(struct tegra_pmc *pmc,
2740 num_clks = pmc->soc->num_pmc_clks;
2741 if (pmc->soc->has_blink_output)
2747 clk_data = devm_kmalloc(pmc->dev, sizeof(*clk_data), GFP_KERNEL);
2751 clk_data->clks = devm_kcalloc(pmc->dev, TEGRA_PMC_CLK_MAX,
2761 for (i = 0; i < pmc->soc->num_pmc_clks; i++) {
2764 data = pmc->soc->pmc_clks_data + i;
2766 clk = tegra_pmc_clk_out_register(pmc, data, PMC_CLK_OUT_CNTRL);
2768 dev_warn(pmc->dev, "unable to register clock %s: %d\n",
2775 dev_warn(pmc->dev,
2784 if (pmc->soc->has_blink_output) {
2785 tegra_pmc_writel(pmc, 0x0, PMC_BLINK_TIMER);
2786 clk = tegra_pmc_clk_gate_register(pmc,
2792 dev_warn(pmc->dev,
2798 clk = tegra_pmc_clk_gate_register(pmc, "pmc_blink",
2803 dev_warn(pmc->dev,
2811 dev_warn(pmc->dev,
2822 dev_warn(pmc->dev, "failed to add pmc clock provider: %d\n",
2844 struct tegra_pmc *pmc = context;
2846 *value = tegra_pmc_readl(pmc, offset);
2852 struct tegra_pmc *pmc = context;
2854 tegra_pmc_writel(pmc, value, offset);
2870 static int tegra_pmc_regmap_init(struct tegra_pmc *pmc)
2875 if (pmc->soc->has_usb_sleepwalk) {
2876 regmap = devm_regmap_init(pmc->dev, NULL, pmc, &usb_sleepwalk_regmap_config);
2879 dev_err(pmc->dev, "failed to allocate register map (%d)\n", err);
2889 pmc->suspend_mode = TEGRA_SUSPEND_NOT_READY;
2903 if (WARN_ON(!pmc->base || !pmc->soc))
2906 err = tegra_pmc_parse_dt(pmc, pdev->dev.of_node);
2922 pmc->wake = devm_ioremap_resource(&pdev->dev, res);
2923 if (IS_ERR(pmc->wake))
2924 return PTR_ERR(pmc->wake);
2926 pmc->wake = base;
2931 pmc->aotag = devm_ioremap_resource(&pdev->dev, res);
2932 if (IS_ERR(pmc->aotag))
2933 return PTR_ERR(pmc->aotag);
2935 pmc->aotag = base;
2940 pmc->scratch = devm_ioremap_resource(&pdev->dev, res);
2941 if (IS_ERR(pmc->scratch))
2942 return PTR_ERR(pmc->scratch);
2944 pmc->scratch = base;
2947 pmc->clk = devm_clk_get_optional(&pdev->dev, "pclk");
2948 if (IS_ERR(pmc->clk))
2949 return dev_err_probe(&pdev->dev, PTR_ERR(pmc->clk),
2993 if (pmc->clk) {
2994 pmc->clk_nb.notifier_call = tegra_pmc_clk_notify_cb;
2995 err = devm_clk_notifier_register(&pdev->dev, pmc->clk,
2996 &pmc->clk_nb);
3003 pmc->rate = clk_get_rate(pmc->clk);
3006 pmc->dev = &pdev->dev;
3008 err = tegra_pmc_init(pmc);
3014 tegra_pmc_init_tsense_reset(pmc);
3016 tegra_pmc_reset_sysfs_init(pmc);
3018 err = tegra_pmc_pinctrl_init(pmc);
3022 err = tegra_pmc_regmap_init(pmc);
3026 err = tegra_powergate_init(pmc, pdev->dev.of_node);
3030 err = tegra_pmc_irq_init(pmc);
3034 mutex_lock(&pmc->powergates_lock);
3035 iounmap(pmc->base);
3036 pmc->base = base;
3037 mutex_unlock(&pmc->powergates_lock);
3039 tegra_pmc_clock_register(pmc, pdev->dev.of_node);
3040 platform_set_drvdata(pdev, pmc);
3044 if (pmc->soc->set_wake_filters)
3045 pmc->soc->set_wake_filters(pmc);
3064 static void wke_32kwritel(struct tegra_pmc *pmc, u32 value, unsigned int offset)
3066 writel(value, pmc->wake + offset);
3070 static void wke_write_wake_level(struct tegra_pmc *pmc, int wake, int level)
3075 value = readl(pmc->wake + offset);
3081 writel(value, pmc->wake + offset);
3084 static void wke_write_wake_levels(struct tegra_pmc *pmc)
3088 for (i = 0; i < pmc->soc->max_wake_events; i++)
3089 wke_write_wake_level(pmc, i, test_bit(i, pmc->wake_cntrl_level_map));
3092 static void wke_clear_sw_wake_status(struct tegra_pmc *pmc)
3094 wke_32kwritel(pmc, 1, WAKE_AOWAKE_SW_STATUS_W_0);
3097 static void wke_read_sw_wake_status(struct tegra_pmc *pmc)
3102 for (i = 0; i < pmc->soc->max_wake_events; i++)
3103 wke_write_wake_level(pmc, i, 0);
3105 wke_clear_sw_wake_status(pmc);
3107 wke_32kwritel(pmc, 1, WAKE_LATCH_SW);
3115 for (i = 0; i < pmc->soc->max_wake_events; i++)
3116 wke_write_wake_level(pmc, i, 1);
3125 wke_32kwritel(pmc, 0, WAKE_LATCH_SW);
3127 bitmap_zero(pmc->wake_sw_status_map, pmc->soc->max_wake_events);
3129 for (i = 0; i < pmc->soc->max_wake_vectors; i++) {
3130 status = readl(pmc->wake + WAKE_AOWAKE_SW_STATUS(i));
3133 set_bit(wake + (i * 32), pmc->wake_sw_status_map);
3137 static void wke_clear_wake_status(struct tegra_pmc *pmc)
3143 for (i = 0; i < pmc->soc->max_wake_vectors; i++) {
3144 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i));
3145 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask;
3148 wke_32kwritel(pmc, 0x1, WAKE_AOWAKE_STATUS_W((i * 32) + wake));
3153 static void tegra186_pmc_process_wake_events(struct tegra_pmc *pmc, unsigned int index,
3158 dev_dbg(pmc->dev, "Wake[%d:%d] status=%#lx\n", (index * 32) + 31, index * 32, status);
3165 irq = irq_find_mapping(pmc->domain, hwirq);
3169 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, IRQ %d\n", hwirq, irq);
3173 dev_dbg(pmc->dev, "Resume caused by WAKE%ld, %s\n", hwirq, desc->action->name);
3183 for (i = 0; i < pmc->soc->max_wake_vectors; i++) {
3184 mask = readl(pmc->wake + WAKE_AOWAKE_TIER2_ROUTING(i));
3185 status = readl(pmc->wake + WAKE_AOWAKE_STATUS_R(i)) & mask;
3187 tegra186_pmc_process_wake_events(pmc, i, status);
3193 wke_read_sw_wake_status(pmc);
3198 bitmap_andnot(pmc->wake_cntrl_level_map, pmc->wake_type_dual_edge_map,
3199 pmc->wake_sw_status_map, pmc->soc->max_wake_events);
3200 bitmap_or(pmc->wake_cntrl_level_map, pmc->wake_cntrl_level_map,
3201 pmc->wake_type_level_map, pmc->soc->max_wake_events);
3204 wke_clear_wake_status(pmc);
3205 wke_write_wake_levels(pmc);
3213 struct tegra_pmc *pmc = dev_get_drvdata(dev);
3215 tegra_pmc_writel(pmc, virt_to_phys(tegra_resume), PMC_SCRATCH41);
3222 struct tegra_pmc *pmc = dev_get_drvdata(dev);
3224 tegra_pmc_writel(pmc, 0x0, PMC_SCRATCH41);
3252 static void tegra20_pmc_init(struct tegra_pmc *pmc)
3257 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3259 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3261 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3263 if (pmc->sysclkreq_high)
3268 if (pmc->corereq_high)
3274 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3277 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3279 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3282 if (pmc->suspend_mode != TEGRA_SUSPEND_NONE) {
3283 osc = DIV_ROUND_UP(pmc->core_osc_time * 8192, 1000000);
3284 pmu = DIV_ROUND_UP(pmc->core_pmu_time * 32768, 1000000);
3285 off = DIV_ROUND_UP(pmc->core_off_time * 32768, 1000000);
3286 tegra_pmc_writel(pmc, ((osc << 8) & 0xff00) | (pmu & 0xff),
3288 tegra_pmc_writel(pmc, off, PMC_COREPWROFF_TIMER);
3292 static void tegra20_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3298 value = tegra_pmc_readl(pmc, PMC_CNTRL);
3305 tegra_pmc_writel(pmc, value, PMC_CNTRL);
3853 static void tegra186_pmc_init(struct tegra_pmc *pmc)
3855 pmc->syscore.suspend = tegra186_pmc_wake_syscore_suspend;
3856 pmc->syscore.resume = tegra186_pmc_wake_syscore_resume;
3858 register_syscore_ops(&pmc->syscore);
3861 static void tegra186_pmc_setup_irq_polarity(struct tegra_pmc *pmc,
3872 dev_err(pmc->dev, "failed to find PMC wake registers\n");
3880 dev_err(pmc->dev, "failed to map PMC wake registers\n");
4273 { .compatible = "nvidia,tegra234-pmc", .data = &tegra234_pmc_soc },
4274 { .compatible = "nvidia,tegra194-pmc", .data = &tegra194_pmc_soc },
4275 { .compatible = "nvidia,tegra186-pmc", .data = &tegra186_pmc_soc },
4276 { .compatible = "nvidia,tegra210-pmc", .data = &tegra210_pmc_soc },
4277 { .compatible = "nvidia,tegra132-pmc", .data = &tegra124_pmc_soc },
4278 { .compatible = "nvidia,tegra124-pmc", .data = &tegra124_pmc_soc },
4279 { .compatible = "nvidia,tegra114-pmc", .data = &tegra114_pmc_soc },
4280 { .compatible = "nvidia,tegra30-pmc", .data = &tegra30_pmc_soc },
4281 { .compatible = "nvidia,tegra20-pmc", .data = &tegra20_pmc_soc },
4294 if (!pmc->soc->supports_core_domain)
4302 if (!pmc->core_domain_registered)
4305 pmc->core_domain_state_synced = true;
4308 mutex_lock(&pmc->powergates_lock);
4310 mutex_unlock(&pmc->powergates_lock);
4318 .name = "tegra-pmc",
4330 static bool __init tegra_pmc_detect_tz_only(struct tegra_pmc *pmc)
4334 saved = readl(pmc->base + pmc->soc->regs->scratch0);
4341 writel(value, pmc->base + pmc->soc->regs->scratch0);
4342 value = readl(pmc->base + pmc->soc->regs->scratch0);
4351 writel(saved, pmc->base + pmc->soc->regs->scratch0);
4368 mutex_init(&pmc->powergates_lock);
4409 pmc->base = ioremap(regs.start, resource_size(®s));
4410 if (!pmc->base) {
4417 pmc->soc = match->data;
4419 if (pmc->soc->maybe_tz_only)
4420 pmc->tz_only = tegra_pmc_detect_tz_only(pmc);
4423 for (i = 0; i < pmc->soc->num_powergates; i++)
4424 if (pmc->soc->powergates[i])
4425 set_bit(i, pmc->powergates_available);
4433 pmc->soc->setup_irq_polarity(pmc, np, invert);