Lines Matching refs:se
17 #include <linux/soc/qcom/geni-se.h>
192 * @se: Pointer to the corresponding serial engine.
196 u32 geni_se_get_qup_hw_version(struct geni_se *se)
198 struct geni_wrapper *wrapper = se->wrapper;
237 static void geni_se_irq_clear(struct geni_se *se)
239 writel_relaxed(0, se->base + SE_GSI_EVENT_EN);
240 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);
241 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR);
242 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR);
243 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR);
244 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN);
249 * @se: Pointer to the concerned serial engine.
256 void geni_se_init(struct geni_se *se, u32 rx_wm, u32 rx_rfr)
260 geni_se_irq_clear(se);
261 geni_se_io_init(se->base);
262 geni_se_io_set_mode(se->base);
264 writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG);
265 writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG);
267 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
269 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
271 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
273 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
277 static void geni_se_select_fifo_mode(struct geni_se *se)
279 u32 proto = geni_se_read_proto(se);
282 geni_se_irq_clear(se);
287 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
291 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
294 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
297 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
300 static void geni_se_select_dma_mode(struct geni_se *se)
302 u32 proto = geni_se_read_proto(se);
305 geni_se_irq_clear(se);
310 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
314 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
317 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
320 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
323 static void geni_se_select_gpi_mode(struct geni_se *se)
327 geni_se_irq_clear(se);
329 writel(0, se->base + SE_IRQ_EN);
331 val = readl(se->base + SE_GENI_M_IRQ_EN);
334 writel(val, se->base + SE_GENI_M_IRQ_EN);
336 writel(GENI_DMA_MODE_EN, se->base + SE_GENI_DMA_MODE_EN);
338 val = readl(se->base + SE_GSI_EVENT_EN);
340 writel(val, se->base + SE_GSI_EVENT_EN);
345 * @se: Pointer to the concerned serial engine.
348 void geni_se_select_mode(struct geni_se *se, enum geni_se_xfer_mode mode)
354 geni_se_select_fifo_mode(se);
357 geni_se_select_dma_mode(se);
360 geni_se_select_gpi_mode(se);
421 * @se: Pointer to the concerned serial engine
431 void geni_se_config_packing(struct geni_se *se, int bpw, int pack_words,
466 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0);
467 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1);
470 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0);
471 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1);
482 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN);
486 static void geni_se_clks_off(struct geni_se *se)
488 struct geni_wrapper *wrapper = se->wrapper;
490 clk_disable_unprepare(se->clk);
497 * @se: Pointer to the concerned serial engine.
501 int geni_se_resources_off(struct geni_se *se)
505 if (has_acpi_companion(se->dev))
508 ret = pinctrl_pm_select_sleep_state(se->dev);
512 geni_se_clks_off(se);
517 static int geni_se_clks_on(struct geni_se *se)
520 struct geni_wrapper *wrapper = se->wrapper;
526 ret = clk_prepare_enable(se->clk);
535 * @se: Pointer to the concerned serial engine.
539 int geni_se_resources_on(struct geni_se *se)
543 if (has_acpi_companion(se->dev))
546 ret = geni_se_clks_on(se);
550 ret = pinctrl_pm_select_default_state(se->dev);
552 geni_se_clks_off(se);
560 * @se: Pointer to the concerned serial engine.
571 int geni_se_clk_tbl_get(struct geni_se *se, unsigned long **tbl)
576 if (se->clk_perf_tbl) {
577 *tbl = se->clk_perf_tbl;
578 return se->num_clk_levels;
581 se->clk_perf_tbl = devm_kcalloc(se->dev, MAX_CLK_PERF_LEVEL,
582 sizeof(*se->clk_perf_tbl),
584 if (!se->clk_perf_tbl)
588 freq = clk_round_rate(se->clk, freq + 1);
589 if (freq <= 0 || freq == se->clk_perf_tbl[i - 1])
591 se->clk_perf_tbl[i] = freq;
593 se->num_clk_levels = i;
594 *tbl = se->clk_perf_tbl;
595 return se->num_clk_levels;
601 * @se: Pointer to the concerned serial engine.
618 int geni_se_clk_freq_match(struct geni_se *se, unsigned long req_freq,
629 num_clk_levels = geni_se_clk_tbl_get(se, &tbl);
668 * @se: Pointer to the concerned serial engine.
674 void geni_se_tx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len)
681 writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET);
682 writel_relaxed(lower_32_bits(iova), se->base + SE_DMA_TX_PTR_L);
683 writel_relaxed(upper_32_bits(iova), se->base + SE_DMA_TX_PTR_H);
684 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR);
685 writel(len, se->base + SE_DMA_TX_LEN);
691 * @se: Pointer to the concerned serial engine.
700 int geni_se_tx_dma_prep(struct geni_se *se, void *buf, size_t len,
703 struct geni_wrapper *wrapper = se->wrapper;
712 geni_se_tx_init_dma(se, *iova, len);
719 * @se: Pointer to the concerned serial engine.
725 void geni_se_rx_init_dma(struct geni_se *se, dma_addr_t iova, size_t len)
732 writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET);
733 writel_relaxed(lower_32_bits(iova), se->base + SE_DMA_RX_PTR_L);
734 writel_relaxed(upper_32_bits(iova), se->base + SE_DMA_RX_PTR_H);
736 writel_relaxed(0, se->base + SE_DMA_RX_ATTR);
737 writel(len, se->base + SE_DMA_RX_LEN);
743 * @se: Pointer to the concerned serial engine.
752 int geni_se_rx_dma_prep(struct geni_se *se, void *buf, size_t len,
755 struct geni_wrapper *wrapper = se->wrapper;
764 geni_se_rx_init_dma(se, *iova, len);
771 * @se: Pointer to the concerned serial engine.
777 void geni_se_tx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
779 struct geni_wrapper *wrapper = se->wrapper;
788 * @se: Pointer to the concerned serial engine.
794 void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len)
796 struct geni_wrapper *wrapper = se->wrapper;
803 int geni_icc_get(struct geni_se *se, const char *icc_ddr)
808 if (has_acpi_companion(se->dev))
811 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
815 se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]);
816 if (IS_ERR(se->icc_paths[i].path))
823 err = PTR_ERR(se->icc_paths[i].path);
825 dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n",
832 int geni_icc_set_bw(struct geni_se *se)
836 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
837 ret = icc_set_bw(se->icc_paths[i].path,
838 se->icc_paths[i].avg_bw, se->icc_paths[i].avg_bw);
840 dev_err_ratelimited(se->dev, "ICC BW voting failed on path '%s': %d\n",
850 void geni_icc_set_tag(struct geni_se *se, u32 tag)
854 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++)
855 icc_set_tag(se->icc_paths[i].path, tag);
860 int geni_icc_enable(struct geni_se *se)
864 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
865 ret = icc_enable(se->icc_paths[i].path);
867 dev_err_ratelimited(se->dev, "ICC enable failed on path '%s': %d\n",
877 int geni_icc_disable(struct geni_se *se)
881 for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) {
882 ret = icc_disable(se->icc_paths[i].path);
884 dev_err_ratelimited(se->dev, "ICC disable failed on path '%s': %d\n",
966 { .compatible = "qcom,geni-se-qup", .data = &qup_desc },
967 { .compatible = "qcom,geni-se-i2c-master-hub", .data = &i2c_master_hub_desc },