Lines Matching refs:base
89 * @base: Base address of this instance of QUP wrapper core
96 void __iomem *base;
200 return readl_relaxed(wrapper->base + QUP_HW_VER_REG);
204 static void geni_se_io_set_mode(void __iomem *base)
208 val = readl_relaxed(base + SE_IRQ_EN);
211 writel_relaxed(val, base + SE_IRQ_EN);
213 val = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
215 writel_relaxed(val, base + SE_GENI_DMA_MODE_EN);
217 writel_relaxed(0, base + SE_GSI_EVENT_EN);
220 static void geni_se_io_init(void __iomem *base)
224 val = readl_relaxed(base + GENI_CGC_CTRL);
226 writel_relaxed(val, base + GENI_CGC_CTRL);
228 val = readl_relaxed(base + SE_DMA_GENERAL_CFG);
231 writel_relaxed(val, base + SE_DMA_GENERAL_CFG);
233 writel_relaxed(DEFAULT_IO_OUTPUT_CTRL_MSK, base + GENI_OUTPUT_CTRL);
234 writel_relaxed(FORCE_DEFAULT, base + GENI_FORCE_DEFAULT_REG);
239 writel_relaxed(0, se->base + SE_GSI_EVENT_EN);
240 writel_relaxed(0xffffffff, se->base + SE_GENI_M_IRQ_CLEAR);
241 writel_relaxed(0xffffffff, se->base + SE_GENI_S_IRQ_CLEAR);
242 writel_relaxed(0xffffffff, se->base + SE_DMA_TX_IRQ_CLR);
243 writel_relaxed(0xffffffff, se->base + SE_DMA_RX_IRQ_CLR);
244 writel_relaxed(0xffffffff, se->base + SE_IRQ_EN);
261 geni_se_io_init(se->base);
262 geni_se_io_set_mode(se->base);
264 writel_relaxed(rx_wm, se->base + SE_GENI_RX_WATERMARK_REG);
265 writel_relaxed(rx_rfr, se->base + SE_GENI_RX_RFR_WATERMARK_REG);
267 val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
269 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
271 val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
273 writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
287 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
291 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
294 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
297 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
310 val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
314 writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
317 val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
320 writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
329 writel(0, se->base + SE_IRQ_EN);
331 val = readl(se->base + SE_GENI_M_IRQ_EN);
334 writel(val, se->base + SE_GENI_M_IRQ_EN);
336 writel(GENI_DMA_MODE_EN, se->base + SE_GENI_DMA_MODE_EN);
338 val = readl(se->base + SE_GSI_EVENT_EN);
340 writel(val, se->base + SE_GSI_EVENT_EN);
466 writel_relaxed(cfg0, se->base + SE_GENI_TX_PACKING_CFG0);
467 writel_relaxed(cfg1, se->base + SE_GENI_TX_PACKING_CFG1);
470 writel_relaxed(cfg0, se->base + SE_GENI_RX_PACKING_CFG0);
471 writel_relaxed(cfg1, se->base + SE_GENI_RX_PACKING_CFG1);
482 writel_relaxed(bpw / 16, se->base + SE_GENI_BYTE_GRAN);
681 writel_relaxed(val, se->base + SE_DMA_TX_IRQ_EN_SET);
682 writel_relaxed(lower_32_bits(iova), se->base + SE_DMA_TX_PTR_L);
683 writel_relaxed(upper_32_bits(iova), se->base + SE_DMA_TX_PTR_H);
684 writel_relaxed(GENI_SE_DMA_EOT_BUF, se->base + SE_DMA_TX_ATTR);
685 writel(len, se->base + SE_DMA_TX_LEN);
732 writel_relaxed(val, se->base + SE_DMA_RX_IRQ_EN_SET);
733 writel_relaxed(lower_32_bits(iova), se->base + SE_DMA_RX_PTR_L);
734 writel_relaxed(upper_32_bits(iova), se->base + SE_DMA_RX_PTR_H);
736 writel_relaxed(0, se->base + SE_DMA_RX_ATTR);
737 writel(len, se->base + SE_DMA_RX_LEN);
905 wrapper->base = devm_platform_ioremap_resource(pdev, 0);
906 if (IS_ERR(wrapper->base))
907 return PTR_ERR(wrapper->base);