Lines Matching defs:svsp
348 bool (*efuse_parsing)(struct svs_platform *svsp);
349 int (*probe)(struct svs_platform *svsp);
424 void (*set_freq_pct)(struct svs_platform *svsp);
425 void (*get_volts)(struct svs_platform *svsp);
484 static u32 svs_readl_relaxed(struct svs_platform *svsp, enum svs_reg_index rg_i)
486 return readl_relaxed(svsp->base + svsp->regs[rg_i]);
489 static void svs_writel_relaxed(struct svs_platform *svsp, u32 val,
492 writel_relaxed(val, svsp->base + svsp->regs[rg_i]);
495 static void svs_switch_bank(struct svs_platform *svsp)
497 struct svs_bank *svsb = svsp->pbank;
499 svs_writel_relaxed(svsp, svsb->core_sel, CORESEL);
624 static void svs_bank_disable_and_restore_default_volts(struct svs_platform *svsp,
633 svsp->pbank = svsb;
634 svs_switch_bank(svsp);
635 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
636 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);
646 struct svs_platform *svsp = (struct svs_platform *)m->private;
651 for (i = 0; i < svsp->efuse_max; i++)
652 if (svsp->efuse && svsp->efuse[i])
654 i, svsp->efuse[i]);
656 for (i = 0; i < svsp->tefuse_max; i++)
657 if (svsp->tefuse)
659 i, svsp->tefuse[i]);
661 for (bank_id = 0, idx = 0; idx < svsp->bank_max; idx++, bank_id++) {
662 svsb = &svsp->banks[idx];
675 svs_reg_addr = (unsigned long)(svsp->base +
676 svsp->regs[j]);
718 struct svs_platform *svsp = dev_get_drvdata(svsb->dev);
734 svs_bank_disable_and_restore_default_volts(svsp, svsb);
783 static int svs_create_debug_cmds(struct svs_platform *svsp)
806 dev_err(svsp->dev, "cannot create %s: %ld\n",
813 svs_dir, svsp,
816 dev_err(svsp->dev, "cannot create %s/%s: %ld\n",
822 for (idx = 0; idx < svsp->bank_max; idx++) {
823 svsb = &svsp->banks[idx];
830 dev_err(svsp->dev, "cannot create %s/%s: %ld\n",
840 dev_err(svsp->dev, "no %s/%s/%s?: %ld\n",
865 static void svs_get_bank_volts_v3(struct svs_platform *svsp)
867 struct svs_bank *svsb = svsp->pbank;
876 vop74 = svs_readl_relaxed(svsp, VOP74);
877 vop30 = svs_readl_relaxed(svsp, VOP30);
957 static void svs_set_bank_freq_pct_v3(struct svs_platform *svsp)
959 struct svs_bank *svsb = svsp->pbank;
1036 svs_writel_relaxed(svsp, freq_pct74, FREQPCT74);
1037 svs_writel_relaxed(svsp, freq_pct30, FREQPCT30);
1040 static void svs_get_bank_volts_v2(struct svs_platform *svsp)
1042 struct svs_bank *svsb = svsp->pbank;
1045 temp = svs_readl_relaxed(svsp, VOP74);
1051 temp = svs_readl_relaxed(svsp, VOP30);
1074 static void svs_set_bank_freq_pct_v2(struct svs_platform *svsp)
1076 struct svs_bank *svsb = svsp->pbank;
1089 svs_writel_relaxed(svsp, freqpct74_val, FREQPCT74);
1090 svs_writel_relaxed(svsp, freqpct30_val, FREQPCT30);
1093 static void svs_set_bank_phase(struct svs_platform *svsp,
1096 struct svs_bank *svsb = svsp->pbank;
1099 svs_switch_bank(svsp);
1103 svs_writel_relaxed(svsp, des_char, DESCHAR);
1108 svs_writel_relaxed(svsp, temp_char, TEMPCHAR);
1112 svs_writel_relaxed(svsp, det_char, DETCHAR);
1114 svs_writel_relaxed(svsp, svsb->dc_config, DCCONFIG);
1115 svs_writel_relaxed(svsp, svsb->age_config, AGECONFIG);
1116 svs_writel_relaxed(svsp, SVSB_RUNCONFIG_DEFAULT, RUNCONFIG);
1118 svsb->set_freq_pct(svsp);
1124 svs_writel_relaxed(svsp, limit_vals, LIMITVALS);
1126 svs_writel_relaxed(svsp, SVSB_DET_WINDOW, DETWINDOW);
1127 svs_writel_relaxed(svsp, SVSB_DET_MAX, CONFIG);
1128 svs_writel_relaxed(svsp, svsb->chk_shift, CHKSHIFT);
1129 svs_writel_relaxed(svsp, svsb->ctl0, CTL0);
1130 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);
1134 svs_writel_relaxed(svsp, svsb->vboot, VBOOT);
1135 svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN);
1136 svs_writel_relaxed(svsp, SVSB_PTPEN_INIT01, SVSEN);
1141 svs_writel_relaxed(svsp, SVSB_INTEN_INIT0x, INTEN);
1142 svs_writel_relaxed(svsp, init2vals, INIT2VALS);
1143 svs_writel_relaxed(svsp, SVSB_PTPEN_INIT02, SVSEN);
1148 svs_writel_relaxed(svsp, ts_calcs, TSCALCS);
1149 svs_writel_relaxed(svsp, SVSB_INTEN_MONVOPEN, INTEN);
1150 svs_writel_relaxed(svsp, SVSB_PTPEN_MON, SVSEN);
1159 static inline void svs_save_bank_register_data(struct svs_platform *svsp,
1162 struct svs_bank *svsb = svsp->pbank;
1166 svsb->reg_data[phase][rg_i] = svs_readl_relaxed(svsp, rg_i);
1169 static inline void svs_error_isr_handler(struct svs_platform *svsp)
1171 struct svs_bank *svsb = svsp->pbank;
1174 __func__, svs_readl_relaxed(svsp, CORESEL));
1176 svs_readl_relaxed(svsp, SVSEN),
1177 svs_readl_relaxed(svsp, INTSTS));
1179 svs_readl_relaxed(svsp, SMSTATE0),
1180 svs_readl_relaxed(svsp, SMSTATE1));
1181 dev_err(svsb->dev, "TEMP = 0x%08x\n", svs_readl_relaxed(svsp, TEMP));
1183 svs_save_bank_register_data(svsp, SVSB_PHASE_ERROR);
1186 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
1187 svs_writel_relaxed(svsp, SVSB_INTSTS_VAL_CLEAN, INTSTS);
1190 static inline void svs_init01_isr_handler(struct svs_platform *svsp)
1192 struct svs_bank *svsb = svsp->pbank;
1195 __func__, svs_readl_relaxed(svsp, VDESIGN74),
1196 svs_readl_relaxed(svsp, VDESIGN30),
1197 svs_readl_relaxed(svsp, DCVALUES));
1199 svs_save_bank_register_data(svsp, SVSB_PHASE_INIT01);
1202 svsb->dc_voffset_in = ~(svs_readl_relaxed(svsp, DCVALUES) &
1209 svsb->age_voffset_in = svs_readl_relaxed(svsp, AGEVALUES) &
1212 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
1213 svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS);
1217 static inline void svs_init02_isr_handler(struct svs_platform *svsp)
1219 struct svs_bank *svsb = svsp->pbank;
1222 __func__, svs_readl_relaxed(svsp, VOP74),
1223 svs_readl_relaxed(svsp, VOP30),
1224 svs_readl_relaxed(svsp, DCVALUES));
1226 svs_save_bank_register_data(svsp, SVSB_PHASE_INIT02);
1229 svsb->get_volts(svsp);
1231 svs_writel_relaxed(svsp, SVSB_PTPEN_OFF, SVSEN);
1232 svs_writel_relaxed(svsp, SVSB_INTSTS_F0_COMPLETE, INTSTS);
1235 static inline void svs_mon_mode_isr_handler(struct svs_platform *svsp)
1237 struct svs_bank *svsb = svsp->pbank;
1239 svs_save_bank_register_data(svsp, SVSB_PHASE_MON);
1242 svsb->get_volts(svsp);
1244 svsb->temp = svs_readl_relaxed(svsp, TEMP) & GENMASK(7, 0);
1245 svs_writel_relaxed(svsp, SVSB_INTSTS_FLD_MONVOP, INTSTS);
1250 struct svs_platform *svsp = data;
1255 for (idx = 0; idx < svsp->bank_max; idx++) {
1256 svsb = &svsp->banks[idx];
1260 svsp->pbank = svsb;
1263 if (svsb->int_st & svs_readl_relaxed(svsp, INTST)) {
1268 svs_switch_bank(svsp);
1269 int_sts = svs_readl_relaxed(svsp, INTSTS);
1270 svs_en = svs_readl_relaxed(svsp, SVSEN);
1274 svs_init01_isr_handler(svsp);
1277 svs_init02_isr_handler(svsp);
1279 svs_mon_mode_isr_handler(svsp);
1281 svs_error_isr_handler(svsp);
1296 static int svs_init01(struct svs_platform *svsp)
1308 for (idx = 0; idx < svsp->bank_max; idx++) {
1309 svsb = &svsp->banks[idx];
1345 for (idx = 0; idx < svsp->bank_max; idx++) {
1346 svsb = &svsp->banks[idx];
1390 for (idx = 0; idx < svsp->bank_max; idx++) {
1391 svsb = &svsp->banks[idx];
1410 svsp->pbank = svsb;
1411 svs_set_bank_phase(svsp, SVSB_PHASE_INIT01);
1424 for (idx = 0; idx < svsp->bank_max; idx++) {
1425 svsb = &svsp->banks[idx];
1465 static int svs_init02(struct svs_platform *svsp)
1472 for (idx = 0; idx < svsp->bank_max; idx++) {
1473 svsb = &svsp->banks[idx];
1480 svsp->pbank = svsb;
1481 svs_set_bank_phase(svsp, SVSB_PHASE_INIT02);
1498 for (idx = 0; idx < svsp->bank_max; idx++) {
1499 svsb = &svsp->banks[idx];
1516 for (idx = 0; idx < svsp->bank_max; idx++) {
1517 svsb = &svsp->banks[idx];
1518 svs_bank_disable_and_restore_default_volts(svsp, svsb);
1524 static void svs_mon_mode(struct svs_platform *svsp)
1530 for (idx = 0; idx < svsp->bank_max; idx++) {
1531 svsb = &svsp->banks[idx];
1537 svsp->pbank = svsb;
1538 svs_set_bank_phase(svsp, SVSB_PHASE_MON);
1543 static int svs_start(struct svs_platform *svsp)
1547 ret = svs_init01(svsp);
1551 ret = svs_init02(svsp);
1555 svs_mon_mode(svsp);
1562 struct svs_platform *svsp = dev_get_drvdata(dev);
1567 for (idx = 0; idx < svsp->bank_max; idx++) {
1568 svsb = &svsp->banks[idx];
1569 svs_bank_disable_and_restore_default_volts(svsp, svsb);
1572 ret = reset_control_assert(svsp->rst);
1574 dev_err(svsp->dev, "cannot assert reset %d\n", ret);
1578 clk_disable_unprepare(svsp->main_clk);
1585 struct svs_platform *svsp = dev_get_drvdata(dev);
1588 ret = clk_prepare_enable(svsp->main_clk);
1590 dev_err(svsp->dev, "cannot enable main_clk, disable svs\n");
1594 ret = reset_control_deassert(svsp->rst);
1596 dev_err(svsp->dev, "cannot deassert reset %d\n", ret);
1600 ret = svs_init02(svsp);
1604 svs_mon_mode(svsp);
1609 dev_err(svsp->dev, "assert reset: %d\n",
1610 reset_control_assert(svsp->rst));
1613 clk_disable_unprepare(svsp->main_clk);
1617 static int svs_bank_resource_setup(struct svs_platform *svsp)
1625 dev_set_drvdata(svsp->dev, svsp);
1627 for (idx = 0; idx < svsp->bank_max; idx++) {
1628 svsb = &svsp->banks[idx];
1653 svsb->dev = devm_kzalloc(svsp->dev, sizeof(*svsb->dev),
1662 dev_set_drvdata(svsb->dev, svsp);
1719 static int svs_get_efuse_data(struct svs_platform *svsp,
1725 cell = nvmem_cell_get(svsp->dev, nvmem_cell_name);
1727 dev_err(svsp->dev, "no \"%s\"? %ld\n",
1734 dev_err(svsp->dev, "cannot read \"%s\" efuse: %ld\n",
1746 static bool svs_mt8192_efuse_parsing(struct svs_platform *svsp)
1752 for (i = 0; i < svsp->efuse_max; i++)
1753 if (svsp->efuse[i])
1754 dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n",
1755 i, svsp->efuse[i]);
1757 if (!svsp->efuse[9]) {
1758 dev_notice(svsp->dev, "svs_efuse[9] = 0x0?\n");
1763 vmin = (svsp->efuse[19] >> 4) & GENMASK(1, 0);
1765 for (idx = 0; idx < svsp->bank_max; idx++) {
1766 svsb = &svsp->banks[idx];
1772 svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0);
1773 svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0);
1774 svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0);
1775 svsb->dcbdet = (svsp->efuse[17]) & GENMASK(7, 0);
1776 svsb->dcmdet = (svsp->efuse[17] >> 8) & GENMASK(7, 0);
1778 svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0);
1779 svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0);
1780 svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0);
1781 svsb->dcbdet = (svsp->efuse[17] >> 16) & GENMASK(7, 0);
1782 svsb->dcmdet = (svsp->efuse[17] >> 24) & GENMASK(7, 0);
1788 ret = svs_get_efuse_data(svsp, "t-calibration-data",
1789 &svsp->tefuse, &svsp->tefuse_max);
1793 for (i = 0; i < svsp->tefuse_max; i++)
1794 if (svsp->tefuse[i] != 0)
1797 if (i == svsp->tefuse_max)
1800 golden_temp = (svsp->tefuse[0] >> 24) & GENMASK(7, 0);
1802 for (idx = 0; idx < svsp->bank_max; idx++) {
1803 svsb = &svsp->banks[idx];
1811 static bool svs_mt8183_efuse_parsing(struct svs_platform *svsp)
1820 for (i = 0; i < svsp->efuse_max; i++)
1821 if (svsp->efuse[i])
1822 dev_info(svsp->dev, "M_HW_RES%d: 0x%08x\n",
1823 i, svsp->efuse[i]);
1825 if (!svsp->efuse[2]) {
1826 dev_notice(svsp->dev, "svs_efuse[2] = 0x0?\n");
1831 ft_pgm = (svsp->efuse[0] >> 4) & GENMASK(3, 0);
1833 for (idx = 0; idx < svsp->bank_max; idx++) {
1834 svsb = &svsp->banks[idx];
1841 svsb->bdes = svsp->efuse[16] & GENMASK(7, 0);
1842 svsb->mdes = (svsp->efuse[16] >> 8) & GENMASK(7, 0);
1843 svsb->dcbdet = (svsp->efuse[16] >> 16) & GENMASK(7, 0);
1844 svsb->dcmdet = (svsp->efuse[16] >> 24) & GENMASK(7, 0);
1845 svsb->mtdes = (svsp->efuse[17] >> 16) & GENMASK(7, 0);
1853 svsb->bdes = svsp->efuse[18] & GENMASK(7, 0);
1854 svsb->mdes = (svsp->efuse[18] >> 8) & GENMASK(7, 0);
1855 svsb->dcbdet = (svsp->efuse[18] >> 16) & GENMASK(7, 0);
1856 svsb->dcmdet = (svsp->efuse[18] >> 24) & GENMASK(7, 0);
1857 svsb->mtdes = svsp->efuse[17] & GENMASK(7, 0);
1865 svsb->bdes = svsp->efuse[4] & GENMASK(7, 0);
1866 svsb->mdes = (svsp->efuse[4] >> 8) & GENMASK(7, 0);
1867 svsb->dcbdet = (svsp->efuse[4] >> 16) & GENMASK(7, 0);
1868 svsb->dcmdet = (svsp->efuse[4] >> 24) & GENMASK(7, 0);
1869 svsb->mtdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0);
1877 svsb->bdes = svsp->efuse[6] & GENMASK(7, 0);
1878 svsb->mdes = (svsp->efuse[6] >> 8) & GENMASK(7, 0);
1879 svsb->dcbdet = (svsp->efuse[6] >> 16) & GENMASK(7, 0);
1880 svsb->dcmdet = (svsp->efuse[6] >> 24) & GENMASK(7, 0);
1881 svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0);
1894 ret = svs_get_efuse_data(svsp, "t-calibration-data",
1895 &svsp->tefuse, &svsp->tefuse_max);
1900 adc_ge_t = (svsp->tefuse[1] >> 22) & GENMASK(9, 0);
1901 adc_oe_t = (svsp->tefuse[1] >> 12) & GENMASK(9, 0);
1903 o_vtsmcu[0] = (svsp->tefuse[0] >> 17) & GENMASK(8, 0);
1904 o_vtsmcu[1] = (svsp->tefuse[0] >> 8) & GENMASK(8, 0);
1905 o_vtsmcu[2] = svsp->tefuse[1] & GENMASK(8, 0);
1906 o_vtsmcu[3] = (svsp->tefuse[2] >> 23) & GENMASK(8, 0);
1907 o_vtsmcu[4] = (svsp->tefuse[2] >> 5) & GENMASK(8, 0);
1908 o_vtsabb = (svsp->tefuse[2] >> 14) & GENMASK(8, 0);
1910 degc_cali = (svsp->tefuse[0] >> 1) & GENMASK(5, 0);
1911 adc_cali_en_t = svsp->tefuse[0] & BIT(0);
1912 o_slope_sign = (svsp->tefuse[0] >> 7) & BIT(0);
1914 ts_id = (svsp->tefuse[1] >> 9) & BIT(0);
1918 o_slope = (svsp->tefuse[0] >> 26) & GENMASK(5, 0);
1935 dev_err(svsp->dev, "bad thermal efuse, no mon mode\n");
1956 for (idx = 0; idx < svsp->bank_max; idx++) {
1957 svsb = &svsp->banks[idx];
1989 for (idx = 0; idx < svsp->bank_max; idx++) {
1990 svsb = &svsp->banks[idx];
1997 static struct device *svs_get_subsys_device(struct svs_platform *svsp,
2005 dev_err(svsp->dev, "cannot find %s node\n", node_name);
2012 dev_err(svsp->dev, "cannot find pdev by %s\n", node_name);
2021 static struct device *svs_add_device_link(struct svs_platform *svsp,
2027 dev = svs_get_subsys_device(svsp, node_name);
2031 sup_link = device_link_add(svsp->dev, dev,
2034 dev_err(svsp->dev, "sup_link is NULL\n");
2044 static int svs_mt8192_platform_probe(struct svs_platform *svsp)
2050 svsp->rst = devm_reset_control_get_optional(svsp->dev, "svs_rst");
2051 if (IS_ERR(svsp->rst))
2052 return dev_err_probe(svsp->dev, PTR_ERR(svsp->rst),
2055 dev = svs_add_device_link(svsp, "lvts");
2057 return dev_err_probe(svsp->dev, PTR_ERR(dev),
2060 for (idx = 0; idx < svsp->bank_max; idx++) {
2061 svsb = &svsp->banks[idx];
2064 svsb->opp_dev = svs_add_device_link(svsp, "gpu");
2066 svsb->opp_dev = svs_get_subsys_device(svsp, "gpu");
2069 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev),
2077 static int svs_mt8183_platform_probe(struct svs_platform *svsp)
2083 dev = svs_add_device_link(svsp, "thermal");
2085 return dev_err_probe(svsp->dev, PTR_ERR(dev),
2088 for (idx = 0; idx < svsp->bank_max; idx++) {
2089 svsb = &svsp->banks[idx];
2097 svsb->opp_dev = svs_add_device_link(svsp, "cci");
2100 svsb->opp_dev = svs_add_device_link(svsp, "gpu");
2108 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev),
2313 struct svs_platform *svsp;
2319 svsp = devm_kzalloc(&pdev->dev, sizeof(*svsp), GFP_KERNEL);
2320 if (!svsp)
2323 svsp->dev = &pdev->dev;
2324 svsp->banks = svsp_data->banks;
2325 svsp->regs = svsp_data->regs;
2326 svsp->bank_max = svsp_data->bank_max;
2328 ret = svsp_data->probe(svsp);
2332 ret = svs_get_efuse_data(svsp, "svs-calibration-data",
2333 &svsp->efuse, &svsp->efuse_max);
2339 if (!svsp_data->efuse_parsing(svsp)) {
2340 dev_err(svsp->dev, "efuse data parsing failed\n");
2345 ret = svs_bank_resource_setup(svsp);
2347 dev_err(svsp->dev, "svs bank resource setup fail: %d\n", ret);
2357 svsp->main_clk = devm_clk_get(svsp->dev, "main");
2358 if (IS_ERR(svsp->main_clk)) {
2359 dev_err(svsp->dev, "failed to get clock: %ld\n",
2360 PTR_ERR(svsp->main_clk));
2361 ret = PTR_ERR(svsp->main_clk);
2365 ret = clk_prepare_enable(svsp->main_clk);
2367 dev_err(svsp->dev, "cannot enable main clk: %d\n", ret);
2371 svsp->base = of_iomap(svsp->dev->of_node, 0);
2372 if (IS_ERR_OR_NULL(svsp->base)) {
2373 dev_err(svsp->dev, "cannot find svs register base\n");
2378 ret = devm_request_threaded_irq(svsp->dev, svsp_irq, NULL, svs_isr,
2379 IRQF_ONESHOT, svsp_data->name, svsp);
2381 dev_err(svsp->dev, "register irq(%d) failed: %d\n",
2386 ret = svs_start(svsp);
2388 dev_err(svsp->dev, "svs start fail: %d\n", ret);
2393 ret = svs_create_debug_cmds(svsp);
2395 dev_err(svsp->dev, "svs create debug cmds fail: %d\n", ret);
2403 iounmap(svsp->base);
2406 clk_disable_unprepare(svsp->main_clk);
2409 if (!IS_ERR_OR_NULL(svsp->tefuse))
2410 kfree(svsp->tefuse);
2413 if (!IS_ERR_OR_NULL(svsp->efuse))
2414 kfree(svsp->efuse);