Lines Matching defs:svsb
497 struct svs_bank *svsb = svsp->pbank;
499 svs_writel_relaxed(svsp, svsb->core_sel, CORESEL);
514 static int svs_sync_bank_volts_from_opp(struct svs_bank *svsb)
519 for (i = 0; i < svsb->opp_count; i++) {
520 opp = dev_pm_opp_find_freq_exact(svsb->opp_dev,
521 svsb->opp_dfreq[i],
524 dev_err(svsb->dev, "cannot find freq = %u (%ld)\n",
525 svsb->opp_dfreq[i], PTR_ERR(opp));
530 svsb->volt[i] = svs_opp_volt_to_bank_volt(opp_u_volt,
531 svsb->volt_step,
532 svsb->volt_base);
539 static int svs_adjust_pm_opp_volts(struct svs_bank *svsb)
544 mutex_lock(&svsb->lock);
550 if (svsb->type == SVSB_HIGH) {
552 opp_stop = svsb->turn_pt;
553 } else if (svsb->type == SVSB_LOW) {
554 opp_start = svsb->turn_pt;
555 opp_stop = svsb->opp_count;
558 opp_stop = svsb->opp_count;
562 if (!IS_ERR_OR_NULL(svsb->tzd)) {
563 ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp);
564 if (ret || (svsb->temp > SVSB_TEMP_UPPER_BOUND &&
565 svsb->temp < SVSB_TEMP_LOWER_BOUND)) {
566 dev_err(svsb->dev, "%s: %d (0x%x), run default volts\n",
567 svsb->tzone_name, ret, svsb->temp);
568 svsb->phase = SVSB_PHASE_ERROR;
571 if (tzone_temp >= svsb->tzone_htemp)
572 temp_voffset += svsb->tzone_htemp_voffset;
573 else if (tzone_temp <= svsb->tzone_ltemp)
574 temp_voffset += svsb->tzone_ltemp_voffset;
577 if (svsb->phase == SVSB_PHASE_MON && (svsb->type == SVSB_HIGH ||
578 svsb->type == SVSB_LOW)) {
580 opp_stop = svsb->opp_count;
586 switch (svsb->phase) {
588 opp_volt = svsb->opp_dvolt[i];
595 svsb_volt = max(svsb->volt[i] + temp_voffset, svsb->vmin);
597 svsb->volt_step,
598 svsb->volt_base);
601 dev_err(svsb->dev, "unknown phase: %u\n", svsb->phase);
606 opp_volt = min(opp_volt, svsb->opp_dvolt[i]);
607 ret = dev_pm_opp_adjust_voltage(svsb->opp_dev,
608 svsb->opp_dfreq[i],
610 svsb->opp_dvolt[i]);
612 dev_err(svsb->dev, "set %uuV fail: %d\n",
619 mutex_unlock(&svsb->lock);
625 struct svs_bank *svsb)
629 if (svsb->mode_support == SVSB_MODE_ALL_DISABLE)
633 svsp->pbank = svsb;
639 svsb->phase = SVSB_PHASE_ERROR;
640 svs_adjust_pm_opp_volts(svsb);
647 struct svs_bank *svsb;
662 svsb = &svsp->banks[idx];
678 svs_reg_addr, svsb->reg_data[i][j]);
690 struct svs_bank *svsb = (struct svs_bank *)m->private;
692 switch (svsb->phase) {
717 struct svs_bank *svsb = file_inode(filp)->i_private;
718 struct svs_platform *svsp = dev_get_drvdata(svsb->dev);
734 svs_bank_disable_and_restore_default_volts(svsp, svsb);
735 svsb->mode_support = SVSB_MODE_ALL_DISABLE;
747 struct svs_bank *svsb = (struct svs_bank *)m->private;
752 ret = thermal_zone_get_temp(svsb->tzd, &tzone_temp);
755 svsb->name, svsb->turn_pt);
758 svsb->name, tzone_temp, svsb->turn_pt);
760 for (i = 0; i < svsb->opp_count; i++) {
761 opp = dev_pm_opp_find_freq_exact(svsb->opp_dev,
762 svsb->opp_dfreq[i], true);
765 svsb->name, svsb->opp_dfreq[i],
771 i, svsb->opp_dfreq[i], i,
774 i, svsb->volt[i], i, svsb->freq_pct[i]);
785 struct svs_bank *svsb;
823 svsb = &svsp->banks[idx];
825 if (svsb->mode_support == SVSB_MODE_ALL_DISABLE)
828 svsb_dir = debugfs_create_dir(svsb->name, svs_dir);
831 d, svsb->name, PTR_ERR(svsb_dir));
837 0664, svsb_dir, svsb,
841 d, svsb->name, svsb_entries[i].name,
867 struct svs_bank *svsb = svsp->pbank;
868 u32 i, j, *vop, vop74, vop30, turn_pt = svsb->turn_pt;
870 u32 middle_index = (svsb->opp_count / 2);
872 if (svsb->phase == SVSB_PHASE_MON &&
873 svsb->volt_flags & SVSB_MON_VOLT_IGNORE)
879 /* Target is to set svsb->volt[] by algorithm */
881 if (svsb->type == SVSB_HIGH) {
887 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
890 } else if (svsb->type == SVSB_LOW) {
892 j = svsb->opp_count - 7;
893 svsb->volt[turn_pt] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30);
895 for (i = j; i < svsb->opp_count; i++) {
899 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
905 svsb->volt[i] = interpolate(svsb->freq_pct[turn_pt],
906 svsb->freq_pct[j],
907 svsb->volt[turn_pt],
908 svsb->volt[j],
909 svsb->freq_pct[i]);
912 if (svsb->type == SVSB_HIGH) {
915 svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, vop30);
921 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
927 svsb->volt[i] = interpolate(svsb->freq_pct[0],
928 svsb->freq_pct[j],
929 svsb->volt[0],
930 svsb->volt[j],
931 svsb->freq_pct[i]);
932 } else if (svsb->type == SVSB_LOW) {
934 for (i = turn_pt; i < svsb->opp_count; i++) {
938 svsb->volt[i] = (*vop >> b_sft) & GENMASK(7, 0);
944 if (svsb->type == SVSB_HIGH) {
946 opp_stop = svsb->turn_pt;
947 } else if (svsb->type == SVSB_LOW) {
948 opp_start = svsb->turn_pt;
949 opp_stop = svsb->opp_count;
953 if (svsb->volt_flags & SVSB_REMOVE_DVTFIXED_VOLT)
954 svsb->volt[i] -= svsb->dvt_fixed;
959 struct svs_bank *svsb = svsp->pbank;
962 u32 middle_index = (svsb->opp_count / 2);
964 for (i = 0; i < svsb->opp_count; i++) {
965 if (svsb->opp_dfreq[i] <= svsb->turn_freq_base) {
966 svsb->turn_pt = i;
971 turn_pt = svsb->turn_pt;
975 if (svsb->type == SVSB_HIGH) {
982 freq_pct30 = svsb->freq_pct[0];
989 *freq_pct |= (svsb->freq_pct[i] << b_sft);
992 } else if (svsb->type == SVSB_LOW) {
997 freq_pct30 = svsb->freq_pct[turn_pt];
999 j = svsb->opp_count - 7;
1000 for (i = j; i < svsb->opp_count; i++) {
1004 *freq_pct |= (svsb->freq_pct[i] << b_sft);
1009 if (svsb->type == SVSB_HIGH) {
1014 freq_pct30 = svsb->freq_pct[0];
1021 *freq_pct |= (svsb->freq_pct[i] << b_sft);
1024 } else if (svsb->type == SVSB_LOW) {
1026 for (i = turn_pt; i < svsb->opp_count; i++) {
1030 *freq_pct |= (svsb->freq_pct[i] << b_sft);
1042 struct svs_bank *svsb = svsp->pbank;
1046 svsb->volt[14] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp);
1047 svsb->volt[12] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp);
1048 svsb->volt[10] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp);
1049 svsb->volt[8] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp);
1052 svsb->volt[6] = FIELD_GET(SVSB_VOPS_FLD_VOP3_7, temp);
1053 svsb->volt[4] = FIELD_GET(SVSB_VOPS_FLD_VOP2_6, temp);
1054 svsb->volt[2] = FIELD_GET(SVSB_VOPS_FLD_VOP1_5, temp);
1055 svsb->volt[0] = FIELD_GET(SVSB_VOPS_FLD_VOP0_4, temp);
1058 svsb->volt[i + 1] = interpolate(svsb->freq_pct[i],
1059 svsb->freq_pct[i + 2],
1060 svsb->volt[i],
1061 svsb->volt[i + 2],
1062 svsb->freq_pct[i + 1]);
1064 svsb->volt[15] = interpolate(svsb->freq_pct[12],
1065 svsb->freq_pct[14],
1066 svsb->volt[12],
1067 svsb->volt[14],
1068 svsb->freq_pct[15]);
1070 for (i = 0; i < svsb->opp_count; i++)
1071 svsb->volt[i] += svsb->volt_od;
1076 struct svs_bank *svsb = svsp->pbank;
1079 freqpct74_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[8]) |
1080 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[10]) |
1081 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[12]) |
1082 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[14]);
1084 freqpct30_val = FIELD_PREP(SVSB_FREQPCTS_FLD_PCT0_4, svsb->freq_pct[0]) |
1085 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT1_5, svsb->freq_pct[2]) |
1086 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT2_6, svsb->freq_pct[4]) |
1087 FIELD_PREP(SVSB_FREQPCTS_FLD_PCT3_7, svsb->freq_pct[6]);
1096 struct svs_bank *svsb = svsp->pbank;
1101 des_char = FIELD_PREP(SVSB_DESCHAR_FLD_BDES, svsb->bdes) |
1102 FIELD_PREP(SVSB_DESCHAR_FLD_MDES, svsb->mdes);
1105 temp_char = FIELD_PREP(SVSB_TEMPCHAR_FLD_VCO, svsb->vco) |
1106 FIELD_PREP(SVSB_TEMPCHAR_FLD_MTDES, svsb->mtdes) |
1107 FIELD_PREP(SVSB_TEMPCHAR_FLD_DVT_FIXED, svsb->dvt_fixed);
1110 det_char = FIELD_PREP(SVSB_DETCHAR_FLD_DCBDET, svsb->dcbdet) |
1111 FIELD_PREP(SVSB_DETCHAR_FLD_DCMDET, svsb->dcmdet);
1114 svs_writel_relaxed(svsp, svsb->dc_config, DCCONFIG);
1115 svs_writel_relaxed(svsp, svsb->age_config, AGECONFIG);
1118 svsb->set_freq_pct(svsp);
1122 FIELD_PREP(SVSB_LIMITVALS_FLD_VMIN, svsb->vmin) |
1123 FIELD_PREP(SVSB_LIMITVALS_FLD_VMAX, svsb->vmax);
1128 svs_writel_relaxed(svsp, svsb->chk_shift, CHKSHIFT);
1129 svs_writel_relaxed(svsp, svsb->ctl0, CTL0);
1134 svs_writel_relaxed(svsp, svsb->vboot, VBOOT);
1139 init2vals = FIELD_PREP(SVSB_INIT2VALS_FLD_AGEVOFFSETIN, svsb->age_voffset_in) |
1140 FIELD_PREP(SVSB_INIT2VALS_FLD_DCVOFFSETIN, svsb->dc_voffset_in);
1146 ts_calcs = FIELD_PREP(SVSB_TSCALCS_FLD_BTS, svsb->bts) |
1147 FIELD_PREP(SVSB_TSCALCS_FLD_MTS, svsb->mts);
1153 dev_err(svsb->dev, "requested unknown target phase: %u\n",
1162 struct svs_bank *svsb = svsp->pbank;
1166 svsb->reg_data[phase][rg_i] = svs_readl_relaxed(svsp, rg_i);
1171 struct svs_bank *svsb = svsp->pbank;
1173 dev_err(svsb->dev, "%s: CORESEL = 0x%08x\n",
1175 dev_err(svsb->dev, "SVSEN = 0x%08x, INTSTS = 0x%08x\n",
1178 dev_err(svsb->dev, "SMSTATE0 = 0x%08x, SMSTATE1 = 0x%08x\n",
1181 dev_err(svsb->dev, "TEMP = 0x%08x\n", svs_readl_relaxed(svsp, TEMP));
1185 svsb->phase = SVSB_PHASE_ERROR;
1192 struct svs_bank *svsb = svsp->pbank;
1194 dev_info(svsb->dev, "%s: VDN74~30:0x%08x~0x%08x, DC:0x%08x\n",
1201 svsb->phase = SVSB_PHASE_INIT01;
1202 svsb->dc_voffset_in = ~(svs_readl_relaxed(svsp, DCVALUES) &
1204 if (svsb->volt_flags & SVSB_INIT01_VOLT_IGNORE ||
1205 (svsb->dc_voffset_in & SVSB_DC_SIGNED_BIT &&
1206 svsb->volt_flags & SVSB_INIT01_VOLT_INC_ONLY))
1207 svsb->dc_voffset_in = 0;
1209 svsb->age_voffset_in = svs_readl_relaxed(svsp, AGEVALUES) &
1214 svsb->core_sel &= ~SVSB_DET_CLK_EN;
1219 struct svs_bank *svsb = svsp->pbank;
1221 dev_info(svsb->dev, "%s: VOP74~30:0x%08x~0x%08x, DC:0x%08x\n",
1228 svsb->phase = SVSB_PHASE_INIT02;
1229 svsb->get_volts(svsp);
1237 struct svs_bank *svsb = svsp->pbank;
1241 svsb->phase = SVSB_PHASE_MON;
1242 svsb->get_volts(svsp);
1244 svsb->temp = svs_readl_relaxed(svsp, TEMP) & GENMASK(7, 0);
1251 struct svs_bank *svsb = NULL;
1256 svsb = &svsp->banks[idx];
1257 WARN(!svsb, "%s: svsb(%s) is null", __func__, svsb->name);
1260 svsp->pbank = svsb;
1263 if (svsb->int_st & svs_readl_relaxed(svsp, INTST)) {
1287 svs_adjust_pm_opp_volts(svsb);
1289 if (svsb->phase == SVSB_PHASE_INIT01 ||
1290 svsb->phase == SVSB_PHASE_INIT02)
1291 complete(&svsb->init_completion);
1298 struct svs_bank *svsb;
1309 svsb = &svsp->banks[idx];
1311 if (!(svsb->mode_support & SVSB_MODE_INIT01))
1314 ret = regulator_enable(svsb->buck);
1316 dev_err(svsb->dev, "%s enable fail: %d\n",
1317 svsb->buck_name, ret);
1322 ret = regulator_set_mode(svsb->buck, REGULATOR_MODE_FAST);
1324 dev_notice(svsb->dev, "set fast mode fail: %d\n", ret);
1326 if (svsb->volt_flags & SVSB_INIT01_PD_REQ) {
1327 if (!pm_runtime_enabled(svsb->opp_dev)) {
1328 pm_runtime_enable(svsb->opp_dev);
1329 svsb->pm_runtime_enabled_count++;
1332 ret = pm_runtime_resume_and_get(svsb->opp_dev);
1334 dev_err(svsb->dev, "mtcmos on fail: %d\n", ret);
1346 svsb = &svsp->banks[idx];
1348 if (!(svsb->mode_support & SVSB_MODE_INIT01))
1356 opp_vboot = svs_bank_volt_to_opp_volt(svsb->vboot,
1357 svsb->volt_step,
1358 svsb->volt_base);
1360 for (i = 0; i < svsb->opp_count; i++) {
1361 opp_freq = svsb->opp_dfreq[i];
1362 if (!search_done && svsb->opp_dvolt[i] <= opp_vboot) {
1363 ret = dev_pm_opp_adjust_voltage(svsb->opp_dev,
1369 dev_err(svsb->dev,
1377 ret = dev_pm_opp_disable(svsb->opp_dev,
1378 svsb->opp_dfreq[i]);
1380 dev_err(svsb->dev,
1382 svsb->opp_dfreq[i], ret);
1391 svsb = &svsp->banks[idx];
1393 if (!(svsb->mode_support & SVSB_MODE_INIT01))
1396 opp_vboot = svs_bank_volt_to_opp_volt(svsb->vboot,
1397 svsb->volt_step,
1398 svsb->volt_base);
1400 buck_volt = regulator_get_voltage(svsb->buck);
1402 dev_err(svsb->dev,
1410 svsp->pbank = svsb;
1414 time_left = wait_for_completion_timeout(&svsb->init_completion,
1417 dev_err(svsb->dev, "init01 completion timeout\n");
1425 svsb = &svsp->banks[idx];
1427 if (!(svsb->mode_support & SVSB_MODE_INIT01))
1430 for (i = 0; i < svsb->opp_count; i++) {
1431 r = dev_pm_opp_enable(svsb->opp_dev,
1432 svsb->opp_dfreq[i]);
1434 dev_err(svsb->dev, "opp %uHz enable fail: %d\n",
1435 svsb->opp_dfreq[i], r);
1438 if (svsb->volt_flags & SVSB_INIT01_PD_REQ) {
1439 r = pm_runtime_put_sync(svsb->opp_dev);
1441 dev_err(svsb->dev, "mtcmos off fail: %d\n", r);
1443 if (svsb->pm_runtime_enabled_count > 0) {
1444 pm_runtime_disable(svsb->opp_dev);
1445 svsb->pm_runtime_enabled_count--;
1449 r = regulator_set_mode(svsb->buck, REGULATOR_MODE_NORMAL);
1451 dev_notice(svsb->dev, "set normal mode fail: %d\n", r);
1453 r = regulator_disable(svsb->buck);
1455 dev_err(svsb->dev, "%s disable fail: %d\n",
1456 svsb->buck_name, r);
1467 struct svs_bank *svsb;
1473 svsb = &svsp->banks[idx];
1475 if (!(svsb->mode_support & SVSB_MODE_INIT02))
1478 reinit_completion(&svsb->init_completion);
1480 svsp->pbank = svsb;
1484 time_left = wait_for_completion_timeout(&svsb->init_completion,
1487 dev_err(svsb->dev, "init02 completion timeout\n");
1499 svsb = &svsp->banks[idx];
1501 if (!(svsb->mode_support & SVSB_MODE_INIT02))
1504 if (svsb->type == SVSB_HIGH || svsb->type == SVSB_LOW) {
1505 if (svs_sync_bank_volts_from_opp(svsb)) {
1506 dev_err(svsb->dev, "sync volt fail\n");
1517 svsb = &svsp->banks[idx];
1518 svs_bank_disable_and_restore_default_volts(svsp, svsb);
1526 struct svs_bank *svsb;
1531 svsb = &svsp->banks[idx];
1533 if (!(svsb->mode_support & SVSB_MODE_MON))
1537 svsp->pbank = svsb;
1563 struct svs_bank *svsb;
1568 svsb = &svsp->banks[idx];
1569 svs_bank_disable_and_restore_default_volts(svsp, svsb);
1619 struct svs_bank *svsb;
1628 svsb = &svsp->banks[idx];
1630 switch (svsb->sw_id) {
1632 svsb->name = "SVSB_CPU_LITTLE";
1635 svsb->name = "SVSB_CPU_BIG";
1638 svsb->name = "SVSB_CCI";
1641 if (svsb->type == SVSB_HIGH)
1642 svsb->name = "SVSB_GPU_HIGH";
1643 else if (svsb->type == SVSB_LOW)
1644 svsb->name = "SVSB_GPU_LOW";
1646 svsb->name = "SVSB_GPU";
1649 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id);
1653 svsb->dev = devm_kzalloc(svsp->dev, sizeof(*svsb->dev),
1655 if (!svsb->dev)
1658 ret = dev_set_name(svsb->dev, "%s", svsb->name);
1662 dev_set_drvdata(svsb->dev, svsp);
1664 ret = devm_pm_opp_of_add_table(svsb->opp_dev);
1666 dev_err(svsb->dev, "add opp table fail: %d\n", ret);
1670 mutex_init(&svsb->lock);
1671 init_completion(&svsb->init_completion);
1673 if (svsb->mode_support & SVSB_MODE_INIT01) {
1674 svsb->buck = devm_regulator_get_optional(svsb->opp_dev,
1675 svsb->buck_name);
1676 if (IS_ERR(svsb->buck)) {
1677 dev_err(svsb->dev, "cannot get \"%s-supply\"\n",
1678 svsb->buck_name);
1679 return PTR_ERR(svsb->buck);
1683 if (!IS_ERR_OR_NULL(svsb->tzone_name)) {
1684 svsb->tzd = thermal_zone_get_zone_by_name(svsb->tzone_name);
1685 if (IS_ERR(svsb->tzd)) {
1686 dev_err(svsb->dev, "cannot get \"%s\" thermal zone\n",
1687 svsb->tzone_name);
1688 return PTR_ERR(svsb->tzd);
1692 count = dev_pm_opp_get_opp_count(svsb->opp_dev);
1693 if (svsb->opp_count != count) {
1694 dev_err(svsb->dev,
1696 svsb->opp_count, count);
1700 for (i = 0, freq = U32_MAX; i < svsb->opp_count; i++, freq--) {
1701 opp = dev_pm_opp_find_freq_floor(svsb->opp_dev, &freq);
1703 dev_err(svsb->dev, "cannot find freq = %ld\n",
1708 svsb->opp_dfreq[i] = freq;
1709 svsb->opp_dvolt[i] = dev_pm_opp_get_voltage(opp);
1710 svsb->freq_pct[i] = percent(svsb->opp_dfreq[i],
1711 svsb->freq_base);
1748 struct svs_bank *svsb;
1766 svsb = &svsp->banks[idx];
1769 svsb->vmin = 0x1e;
1771 if (svsb->type == SVSB_LOW) {
1772 svsb->mtdes = svsp->efuse[10] & GENMASK(7, 0);
1773 svsb->bdes = (svsp->efuse[10] >> 16) & GENMASK(7, 0);
1774 svsb->mdes = (svsp->efuse[10] >> 24) & GENMASK(7, 0);
1775 svsb->dcbdet = (svsp->efuse[17]) & GENMASK(7, 0);
1776 svsb->dcmdet = (svsp->efuse[17] >> 8) & GENMASK(7, 0);
1777 } else if (svsb->type == SVSB_HIGH) {
1778 svsb->mtdes = svsp->efuse[9] & GENMASK(7, 0);
1779 svsb->bdes = (svsp->efuse[9] >> 16) & GENMASK(7, 0);
1780 svsb->mdes = (svsp->efuse[9] >> 24) & GENMASK(7, 0);
1781 svsb->dcbdet = (svsp->efuse[17] >> 16) & GENMASK(7, 0);
1782 svsb->dcmdet = (svsp->efuse[17] >> 24) & GENMASK(7, 0);
1785 svsb->vmax += svsb->dvt_fixed;
1803 svsb = &svsp->banks[idx];
1804 svsb->mts = 500;
1805 svsb->bts = (((500 * golden_temp + 250460) / 1000) - 25) * 4;
1813 struct svs_bank *svsb;
1834 svsb = &svsp->banks[idx];
1837 svsb->volt_flags |= SVSB_INIT01_VOLT_IGNORE;
1839 switch (svsb->sw_id) {
1841 svsb->bdes = svsp->efuse[16] & GENMASK(7, 0);
1842 svsb->mdes = (svsp->efuse[16] >> 8) & GENMASK(7, 0);
1843 svsb->dcbdet = (svsp->efuse[16] >> 16) & GENMASK(7, 0);
1844 svsb->dcmdet = (svsp->efuse[16] >> 24) & GENMASK(7, 0);
1845 svsb->mtdes = (svsp->efuse[17] >> 16) & GENMASK(7, 0);
1848 svsb->volt_od += 10;
1850 svsb->volt_od += 2;
1853 svsb->bdes = svsp->efuse[18] & GENMASK(7, 0);
1854 svsb->mdes = (svsp->efuse[18] >> 8) & GENMASK(7, 0);
1855 svsb->dcbdet = (svsp->efuse[18] >> 16) & GENMASK(7, 0);
1856 svsb->dcmdet = (svsp->efuse[18] >> 24) & GENMASK(7, 0);
1857 svsb->mtdes = svsp->efuse[17] & GENMASK(7, 0);
1860 svsb->volt_od += 15;
1862 svsb->volt_od += 12;
1865 svsb->bdes = svsp->efuse[4] & GENMASK(7, 0);
1866 svsb->mdes = (svsp->efuse[4] >> 8) & GENMASK(7, 0);
1867 svsb->dcbdet = (svsp->efuse[4] >> 16) & GENMASK(7, 0);
1868 svsb->dcmdet = (svsp->efuse[4] >> 24) & GENMASK(7, 0);
1869 svsb->mtdes = (svsp->efuse[5] >> 16) & GENMASK(7, 0);
1872 svsb->volt_od += 10;
1874 svsb->volt_od += 2;
1877 svsb->bdes = svsp->efuse[6] & GENMASK(7, 0);
1878 svsb->mdes = (svsp->efuse[6] >> 8) & GENMASK(7, 0);
1879 svsb->dcbdet = (svsp->efuse[6] >> 16) & GENMASK(7, 0);
1880 svsb->dcmdet = (svsp->efuse[6] >> 24) & GENMASK(7, 0);
1881 svsb->mtdes = svsp->efuse[5] & GENMASK(7, 0);
1884 svsb->freq_base = 800000000; /* 800MHz */
1885 svsb->dvt_fixed = 2;
1889 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id);
1957 svsb = &svsp->banks[idx];
1958 svsb->mts = mts;
1960 switch (svsb->sw_id) {
1974 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id);
1983 svsb->bts = (temp0 + temp2 - 250) * 4 / 10;
1990 svsb = &svsp->banks[idx];
1991 svsb->mode_support &= ~SVSB_MODE_MON;
2047 struct svs_bank *svsb;
2061 svsb = &svsp->banks[idx];
2063 if (svsb->type == SVSB_HIGH)
2064 svsb->opp_dev = svs_add_device_link(svsp, "gpu");
2065 else if (svsb->type == SVSB_LOW)
2066 svsb->opp_dev = svs_get_subsys_device(svsp, "gpu");
2068 if (IS_ERR(svsb->opp_dev))
2069 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev),
2080 struct svs_bank *svsb;
2089 svsb = &svsp->banks[idx];
2091 switch (svsb->sw_id) {
2094 svsb->opp_dev = get_cpu_device(svsb->cpu_id);
2097 svsb->opp_dev = svs_add_device_link(svsp, "cci");
2100 svsb->opp_dev = svs_add_device_link(svsp, "gpu");
2103 dev_err(svsb->dev, "unknown sw_id: %u\n", svsb->sw_id);
2107 if (IS_ERR(svsb->opp_dev))
2108 return dev_err_probe(svsp->dev, PTR_ERR(svsb->opp_dev),