Lines Matching defs:phase
178 * enum svsb_phase - svs bank phase enumeration
183 * @SVSB_PHASE_MAX: total number of svs bank phase (debug purpose)
185 * Each svs bank has its own independent phase and we enable each svs bank by
186 * running their phase orderly. However, when svs bank encounters unexpected
189 * svs bank general phase-enabled order:
367 * @phase: bank current phase
369 * @reg_data: bank register data in different phase for debug purpose
429 enum svsb_phase phase;
568 svsb->phase = SVSB_PHASE_ERROR;
577 if (svsb->phase == SVSB_PHASE_MON && (svsb->type == SVSB_HIGH ||
586 switch (svsb->phase) {
601 dev_err(svsb->dev, "unknown phase: %u\n", svsb->phase);
639 svsb->phase = SVSB_PHASE_ERROR;
692 switch (svsb->phase) {
872 if (svsb->phase == SVSB_PHASE_MON &&
1153 dev_err(svsb->dev, "requested unknown target phase: %u\n",
1160 enum svsb_phase phase)
1166 svsb->reg_data[phase][rg_i] = svs_readl_relaxed(svsp, rg_i);
1185 svsb->phase = SVSB_PHASE_ERROR;
1201 svsb->phase = SVSB_PHASE_INIT01;
1228 svsb->phase = SVSB_PHASE_INIT02;
1241 svsb->phase = SVSB_PHASE_MON;
1289 if (svsb->phase == SVSB_PHASE_INIT01 ||
1290 svsb->phase == SVSB_PHASE_INIT02)