Lines Matching refs:wrp
1341 int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
1342 int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
1389 int (*init_reg_clock)(struct pmic_wrapper *wrp);
1390 int (*init_soc_specific)(struct pmic_wrapper *wrp);
1393 static u32 pwrap_readl(struct pmic_wrapper *wrp, enum pwrap_regs reg)
1395 return readl(wrp->base + wrp->master->regs[reg]);
1398 static void pwrap_writel(struct pmic_wrapper *wrp, u32 val, enum pwrap_regs reg)
1400 writel(val, wrp->base + wrp->master->regs[reg]);
1403 static u32 pwrap_get_fsm_state(struct pmic_wrapper *wrp)
1407 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1408 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
1414 static bool pwrap_is_fsm_idle(struct pmic_wrapper *wrp)
1416 return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_IDLE;
1419 static bool pwrap_is_fsm_vldclr(struct pmic_wrapper *wrp)
1421 return pwrap_get_fsm_state(wrp) == PWRAP_WACS_FSM_WFVLDCLR;
1432 static inline void pwrap_leave_fsm_vldclr(struct pmic_wrapper *wrp)
1434 if (pwrap_is_fsm_vldclr(wrp))
1435 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1438 static bool pwrap_is_sync_idle(struct pmic_wrapper *wrp)
1440 return pwrap_readl(wrp, PWRAP_WACS2_RDATA) & PWRAP_STATE_SYNC_IDLE0;
1443 static bool pwrap_is_fsm_idle_and_sync_idle(struct pmic_wrapper *wrp)
1445 u32 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1451 static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1457 ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp,
1460 pwrap_leave_fsm_vldclr(wrp);
1464 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
1468 pwrap_writel(wrp, val, PWRAP_WACS2_CMD);
1470 ret = readx_poll_timeout(pwrap_is_fsm_vldclr, wrp, tmp, tmp,
1475 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
1476 val = pwrap_readl(wrp, PWRAP_SWINF_2_RDATA_31_0);
1478 val = pwrap_readl(wrp, PWRAP_WACS2_RDATA);
1481 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1486 static int pwrap_read32(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1493 ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp,
1497 pwrap_leave_fsm_vldclr(wrp);
1501 pwrap_writel(wrp, ((msb << 30) | (adr << 16)),
1504 ret = readx_poll_timeout(pwrap_is_fsm_vldclr, wrp, tmp, tmp,
1509 *rdata += (PWRAP_GET_WACS_RDATA(pwrap_readl(wrp,
1512 pwrap_writel(wrp, 1, PWRAP_WACS2_VLDCLR);
1518 static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
1520 return wrp->slave->regops->pwrap_read(wrp, adr, rdata);
1523 static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1528 ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp,
1531 pwrap_leave_fsm_vldclr(wrp);
1535 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB)) {
1536 pwrap_writel(wrp, wdata, PWRAP_SWINF_2_WDATA_31_0);
1537 pwrap_writel(wrp, BIT(29) | adr, PWRAP_WACS2_CMD);
1539 pwrap_writel(wrp, BIT(31) | ((adr >> 1) << 16) | wdata,
1546 static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1552 ret = readx_poll_timeout(pwrap_is_fsm_idle, wrp, tmp, tmp,
1555 pwrap_leave_fsm_vldclr(wrp);
1559 pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) |
1571 pwrap_read(wrp, adr, &rdata);
1577 static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
1579 return wrp->slave->regops->pwrap_write(wrp, adr, wdata);
1592 static bool pwrap_pmic_read_test(struct pmic_wrapper *wrp, const u32 *dew_regs,
1598 pwrap_read(wrp, dew_regs[PWRAP_DEW_READ_TEST], &rdata);
1604 static int pwrap_reset_spislave(struct pmic_wrapper *wrp)
1609 pwrap_writel(wrp, 0, PWRAP_HIPRIO_ARB_EN);
1610 pwrap_writel(wrp, 0, PWRAP_WRAP_EN);
1611 pwrap_writel(wrp, 1, PWRAP_MUX_SEL);
1612 pwrap_writel(wrp, 1, PWRAP_MAN_EN);
1613 pwrap_writel(wrp, 0, PWRAP_DIO_EN);
1615 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSL,
1617 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
1619 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_CSH,
1623 pwrap_writel(wrp, wrp->master->spi_w | PWRAP_MAN_CMD_OP_OUTS,
1626 ret = readx_poll_timeout(pwrap_is_sync_idle, wrp, tmp, tmp,
1629 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1633 pwrap_writel(wrp, 0, PWRAP_MAN_EN);
1634 pwrap_writel(wrp, 0, PWRAP_MUX_SEL);
1645 static int pwrap_init_sidly(struct pmic_wrapper *wrp)
1655 pwrap_writel(wrp, i, PWRAP_SIDLY);
1656 read_ok = pwrap_pmic_read_test(wrp, wrp->slave->dew_regs,
1659 dev_dbg(wrp->dev, "[Read Test] pass, SIDLY=%x\n", i);
1665 dev_err(wrp->dev, "sidly pass range 0x%x not continuous\n",
1670 pwrap_writel(wrp, dly[pass], PWRAP_SIDLY);
1675 static int pwrap_init_dual_io(struct pmic_wrapper *wrp)
1682 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_DIO_EN], 1);
1683 if (wrp->slave->comp_dew_regs)
1684 pwrap_write(wrp, wrp->slave->comp_dew_regs[PWRAP_DEW_DIO_EN], 1);
1687 ret = readx_poll_timeout(pwrap_is_fsm_idle_and_sync_idle, wrp, tmp, tmp,
1690 dev_err(wrp->dev, "%s fail, ret=%d\n", __func__, ret);
1694 pwrap_writel(wrp, 1, PWRAP_DIO_EN);
1697 read_ok = pwrap_pmic_read_test(wrp, wrp->slave->dew_regs, PWRAP_DEW_READ_TEST_VAL);
1698 if (wrp->slave->comp_dew_regs)
1699 comp_read_ok = pwrap_pmic_read_test(wrp, wrp->slave->comp_dew_regs,
1702 dev_err(wrp->dev, "Read failed on DIO mode. Main PMIC %s%s\n",
1704 wrp->slave->comp_dew_regs && !comp_read_ok ?
1716 static void pwrap_init_chip_select_ext(struct pmic_wrapper *wrp, u8 hext_write,
1725 pwrap_writel(wrp, hext_write, PWRAP_CSHEXT_WRITE);
1726 pwrap_writel(wrp, hext_read, PWRAP_CSHEXT_READ);
1733 pwrap_writel(wrp, lext_start, PWRAP_CSLEXT_START);
1734 pwrap_writel(wrp, lext_end, PWRAP_CSLEXT_END);
1737 static int pwrap_common_init_reg_clock(struct pmic_wrapper *wrp)
1739 switch (wrp->master->type) {
1741 if (wrp->slave->type == PMIC_MT6331) {
1742 const u32 *dew_regs = wrp->slave->dew_regs;
1744 pwrap_write(wrp, dew_regs[PWRAP_DEW_RDDMY_NO], 0x8);
1746 if (wrp->slave->comp_type == PMIC_MT6332) {
1747 dew_regs = wrp->slave->comp_dew_regs;
1748 pwrap_write(wrp, dew_regs[PWRAP_DEW_RDDMY_NO], 0x8);
1751 pwrap_writel(wrp, 0x88, PWRAP_RDDMY);
1752 pwrap_init_chip_select_ext(wrp, 15, 15, 15, 15);
1755 pwrap_init_chip_select_ext(wrp, 0, 4, 2, 2);
1758 pwrap_writel(wrp, 0x4, PWRAP_CSHEXT);
1759 pwrap_init_chip_select_ext(wrp, 0, 4, 0, 0);
1768 static int pwrap_mt2701_init_reg_clock(struct pmic_wrapper *wrp)
1770 switch (wrp->slave->type) {
1772 pwrap_writel(wrp, 0xc, PWRAP_RDDMY);
1773 pwrap_init_chip_select_ext(wrp, 4, 0, 2, 2);
1777 pwrap_writel(wrp, 0x8, PWRAP_RDDMY);
1778 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_RDDMY_NO],
1780 pwrap_init_chip_select_ext(wrp, 5, 0, 2, 2);
1789 static bool pwrap_is_cipher_ready(struct pmic_wrapper *wrp)
1791 return pwrap_readl(wrp, PWRAP_CIPHER_RDY) & 1;
1794 static bool __pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp, const u32 *dew_regs)
1799 ret = pwrap_read(wrp, dew_regs[PWRAP_DEW_CIPHER_RDY], &rdata);
1807 static bool pwrap_is_pmic_cipher_ready(struct pmic_wrapper *wrp)
1809 bool ret = __pwrap_is_pmic_cipher_ready(wrp, wrp->slave->dew_regs);
1815 if (wrp->slave->comp_dew_regs)
1816 ret = __pwrap_is_pmic_cipher_ready(wrp, wrp->slave->comp_dew_regs);
1821 static void pwrap_config_cipher(struct pmic_wrapper *wrp, const u32 *dew_regs)
1823 pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x1);
1824 pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_SWRST], 0x0);
1825 pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_KEY_SEL], 0x1);
1826 pwrap_write(wrp, dew_regs[PWRAP_DEW_CIPHER_IV_SEL], 0x2);
1829 static int pwrap_init_cipher(struct pmic_wrapper *wrp)
1835 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_SWRST);
1836 pwrap_writel(wrp, 0x0, PWRAP_CIPHER_SWRST);
1837 pwrap_writel(wrp, 0x1, PWRAP_CIPHER_KEY_SEL);
1838 pwrap_writel(wrp, 0x2, PWRAP_CIPHER_IV_SEL);
1840 switch (wrp->master->type) {
1842 pwrap_writel(wrp, 1, PWRAP_CIPHER_LOAD);
1843 pwrap_writel(wrp, 1, PWRAP_CIPHER_START);
1854 pwrap_writel(wrp, 1, PWRAP_CIPHER_EN);
1857 pwrap_writel(wrp, 0, PWRAP_CIPHER_EN);
1866 pwrap_config_cipher(wrp, wrp->slave->dew_regs);
1869 if (wrp->slave->comp_type > 0)
1870 pwrap_config_cipher(wrp, wrp->slave->comp_dew_regs);
1872 switch (wrp->slave->type) {
1874 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_LOAD],
1876 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_START],
1882 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_EN],
1890 ret = readx_poll_timeout(pwrap_is_cipher_ready, wrp, tmp, tmp,
1893 dev_err(wrp->dev, "cipher data ready@AP fail, ret=%d\n", ret);
1898 ret = readx_poll_timeout(pwrap_is_pmic_cipher_ready, wrp, tmp, tmp,
1901 dev_err(wrp->dev,
1907 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CIPHER_MODE], 0x1);
1908 ret = readx_poll_timeout(pwrap_is_fsm_idle_and_sync_idle, wrp, tmp, tmp,
1911 dev_err(wrp->dev, "cipher mode idle fail, ret=%d\n", ret);
1915 pwrap_writel(wrp, 1, PWRAP_CIPHER_MODE);
1918 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1920 pwrap_read(wrp, wrp->slave->dew_regs[PWRAP_DEW_WRITE_TEST],
1923 dev_err(wrp->dev, "rdata=0x%04X\n", rdata);
1930 static int pwrap_init_security(struct pmic_wrapper *wrp)
1936 ret = pwrap_init_cipher(wrp);
1941 ret = pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1);
1942 if (ret == 0 && wrp->slave->comp_dew_regs)
1943 ret = pwrap_write(wrp, wrp->slave->comp_dew_regs[PWRAP_DEW_CRC_EN], 0x1);
1945 pwrap_writel(wrp, 0x1, PWRAP_CRC_EN);
1946 pwrap_writel(wrp, 0x0, PWRAP_SIG_MODE);
1949 crc_val = wrp->slave->dew_regs[PWRAP_DEW_CRC_VAL];
1950 if (wrp->slave->comp_dew_regs)
1951 crc_val |= wrp->slave->comp_dew_regs[PWRAP_DEW_CRC_VAL] << 16;
1953 pwrap_writel(wrp, crc_val, PWRAP_SIG_ADR);
1956 pwrap_writel(wrp,
1957 wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
1962 static int pwrap_mt8135_init_soc_specific(struct pmic_wrapper *wrp)
1965 pwrap_writel(wrp, 0x1, PWRAP_EVENT_IN_EN);
1966 pwrap_writel(wrp, 0xffff, PWRAP_EVENT_DST_EN);
1967 writel(0x7f, wrp->bridge_base + PWRAP_MT8135_BRIDGE_IORD_ARB_EN);
1968 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS3_EN);
1969 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WACS4_EN);
1970 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_UNIT);
1971 writel(0xffff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_WDT_SRC_EN);
1972 writel(0x1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_TIMER_EN);
1973 writel(0x7ff, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INT_EN);
1976 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
1978 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
1980 dev_err(wrp->dev, "enable dewrap fail\n");
1987 static int pwrap_mt8173_init_soc_specific(struct pmic_wrapper *wrp)
1990 if (pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_OUT_EN],
1992 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_EVENT_SRC_EN],
1994 dev_err(wrp->dev, "enable dewrap fail\n");
2001 static int pwrap_mt2701_init_soc_specific(struct pmic_wrapper *wrp)
2004 switch (wrp->slave->type) {
2006 pwrap_writel(wrp, 0x076c, PWRAP_ADC_CMD_ADDR);
2007 pwrap_writel(wrp, 0x8000, PWRAP_PWRAP_ADC_CMD);
2008 pwrap_writel(wrp, 0x072c, PWRAP_ADC_RDY_ADDR);
2009 pwrap_writel(wrp, 0x072e, PWRAP_ADC_RDATA_ADDR1);
2010 pwrap_writel(wrp, 0x0730, PWRAP_ADC_RDATA_ADDR2);
2019 static int pwrap_mt6795_init_soc_specific(struct pmic_wrapper *wrp)
2021 pwrap_writel(wrp, 0xf, PWRAP_STAUPD_GRPEN);
2023 if (wrp->slave->type == PMIC_MT6331)
2024 pwrap_writel(wrp, 0x1b4, PWRAP_EINT_STA0_ADR);
2026 if (wrp->slave->comp_type == PMIC_MT6332)
2027 pwrap_writel(wrp, 0x8112, PWRAP_EINT_STA1_ADR);
2032 static int pwrap_mt7622_init_soc_specific(struct pmic_wrapper *wrp)
2034 pwrap_writel(wrp, 0, PWRAP_STAUPD_PRD);
2036 pwrap_writel(wrp, 0x8000000, PWRAP_SPI2_CTRL);
2041 static int pwrap_mt8183_init_soc_specific(struct pmic_wrapper *wrp)
2043 pwrap_writel(wrp, 0xf5, PWRAP_STAUPD_GRPEN);
2045 pwrap_write(wrp, wrp->slave->dew_regs[PWRAP_DEW_CRC_EN], 0x1);
2046 pwrap_writel(wrp, 1, PWRAP_CRC_EN);
2047 pwrap_writel(wrp, 0x416, PWRAP_SIG_ADR);
2048 pwrap_writel(wrp, 0x42e, PWRAP_EINT_STA0_ADR);
2050 pwrap_writel(wrp, 1, PWRAP_WACS_P2P_EN);
2051 pwrap_writel(wrp, 1, PWRAP_WACS_MD32_EN);
2052 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_P2P);
2053 pwrap_writel(wrp, 1, PWRAP_INIT_DONE_MD32);
2058 static int pwrap_init(struct pmic_wrapper *wrp)
2062 if (wrp->rstc)
2063 reset_control_reset(wrp->rstc);
2064 if (wrp->rstc_bridge)
2065 reset_control_reset(wrp->rstc_bridge);
2067 switch (wrp->master->type) {
2072 pwrap_writel(wrp, 3, PWRAP_DCM_EN);
2073 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
2079 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
2081 ret = pwrap_reset_spislave(wrp);
2086 pwrap_writel(wrp, 1, PWRAP_WRAP_EN);
2088 pwrap_writel(wrp, wrp->master->arb_en_all, PWRAP_HIPRIO_ARB_EN);
2090 pwrap_writel(wrp, 1, PWRAP_WACS2_EN);
2092 ret = wrp->master->init_reg_clock(wrp);
2096 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SPI)) {
2098 ret = pwrap_init_sidly(wrp);
2103 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_DUALIO)) {
2105 ret = pwrap_init_dual_io(wrp);
2110 if (HAS_CAP(wrp->slave->caps, PWRAP_SLV_CAP_SECURITY)) {
2112 ret = pwrap_init_security(wrp);
2117 if (wrp->master->type == PWRAP_MT8135)
2118 pwrap_writel(wrp, 0x7, PWRAP_RRARB_EN);
2120 pwrap_writel(wrp, 0x1, PWRAP_WACS0_EN);
2121 pwrap_writel(wrp, 0x1, PWRAP_WACS1_EN);
2122 pwrap_writel(wrp, 0x1, PWRAP_WACS2_EN);
2123 pwrap_writel(wrp, 0x5, PWRAP_STAUPD_PRD);
2124 pwrap_writel(wrp, 0xff, PWRAP_STAUPD_GRPEN);
2126 if (wrp->master->init_soc_specific) {
2127 ret = wrp->master->init_soc_specific(wrp);
2133 pwrap_writel(wrp, 1, PWRAP_INIT_DONE2);
2134 pwrap_writel(wrp, 1, PWRAP_INIT_DONE0);
2135 pwrap_writel(wrp, 1, PWRAP_INIT_DONE1);
2137 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
2138 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE3);
2139 writel(1, wrp->bridge_base + PWRAP_MT8135_BRIDGE_INIT_DONE4);
2148 struct pmic_wrapper *wrp = dev_id;
2150 rdata = pwrap_readl(wrp, PWRAP_INT_FLG);
2151 dev_err(wrp->dev, "unexpected interrupt int=0x%x\n", rdata);
2152 pwrap_writel(wrp, 0xffffffff, PWRAP_INT_CLR);
2154 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN)) {
2155 rdata = pwrap_readl(wrp, PWRAP_INT1_FLG);
2156 dev_err(wrp->dev, "unexpected interrupt int1=0x%x\n", rdata);
2157 pwrap_writel(wrp, 0xffffffff, PWRAP_INT1_CLR);
2474 struct pmic_wrapper *wrp;
2486 wrp = devm_kzalloc(&pdev->dev, sizeof(*wrp), GFP_KERNEL);
2487 if (!wrp)
2490 platform_set_drvdata(pdev, wrp);
2492 wrp->master = of_device_get_match_data(&pdev->dev);
2493 wrp->slave = of_slave_id->data;
2494 wrp->dev = &pdev->dev;
2496 wrp->base = devm_platform_ioremap_resource_byname(pdev, "pwrap");
2497 if (IS_ERR(wrp->base))
2498 return PTR_ERR(wrp->base);
2500 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_RESET)) {
2501 wrp->rstc = devm_reset_control_get(wrp->dev, "pwrap");
2502 if (IS_ERR(wrp->rstc)) {
2503 ret = PTR_ERR(wrp->rstc);
2504 dev_dbg(wrp->dev, "cannot get pwrap reset: %d\n", ret);
2509 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_BRIDGE)) {
2510 wrp->bridge_base = devm_platform_ioremap_resource_byname(pdev, "pwrap-bridge");
2511 if (IS_ERR(wrp->bridge_base))
2512 return PTR_ERR(wrp->bridge_base);
2514 wrp->rstc_bridge = devm_reset_control_get(wrp->dev,
2516 if (IS_ERR(wrp->rstc_bridge)) {
2517 ret = PTR_ERR(wrp->rstc_bridge);
2518 dev_dbg(wrp->dev,
2524 wrp->clk_spi = devm_clk_get(wrp->dev, "spi");
2525 if (IS_ERR(wrp->clk_spi)) {
2526 dev_dbg(wrp->dev, "failed to get clock: %ld\n",
2527 PTR_ERR(wrp->clk_spi));
2528 return PTR_ERR(wrp->clk_spi);
2531 wrp->clk_wrap = devm_clk_get(wrp->dev, "wrap");
2532 if (IS_ERR(wrp->clk_wrap)) {
2533 dev_dbg(wrp->dev, "failed to get clock: %ld\n",
2534 PTR_ERR(wrp->clk_wrap));
2535 return PTR_ERR(wrp->clk_wrap);
2538 wrp->clk_sys = devm_clk_get_optional(wrp->dev, "sys");
2539 if (IS_ERR(wrp->clk_sys)) {
2540 return dev_err_probe(wrp->dev, PTR_ERR(wrp->clk_sys),
2542 wrp->clk_sys);
2545 wrp->clk_tmr = devm_clk_get_optional(wrp->dev, "tmr");
2546 if (IS_ERR(wrp->clk_tmr)) {
2547 return dev_err_probe(wrp->dev, PTR_ERR(wrp->clk_tmr),
2549 wrp->clk_tmr);
2552 ret = clk_prepare_enable(wrp->clk_spi);
2556 ret = clk_prepare_enable(wrp->clk_wrap);
2560 ret = clk_prepare_enable(wrp->clk_sys);
2564 ret = clk_prepare_enable(wrp->clk_tmr);
2569 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_DCM)) {
2570 pwrap_writel(wrp, 1, PWRAP_DCM_EN);
2571 pwrap_writel(wrp, 0, PWRAP_DCM_DBC_PRD);
2578 if (!pwrap_readl(wrp, PWRAP_INIT_DONE2)) {
2579 ret = pwrap_init(wrp);
2581 dev_dbg(wrp->dev, "init failed with %d\n", ret);
2586 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
2588 else if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB_MT8186))
2593 if (!(pwrap_readl(wrp, PWRAP_WACS2_RDATA) & mask_done)) {
2594 dev_dbg(wrp->dev, "initialization isn't finished\n");
2600 if (!HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
2601 pwrap_writel(wrp, 0xf, PWRAP_WDT_UNIT);
2607 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN);
2608 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_WDT_SRC1))
2609 pwrap_writel(wrp, wrp->master->wdt_src, PWRAP_WDT_SRC_EN_1);
2611 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_ARB))
2612 pwrap_writel(wrp, 0x3, PWRAP_TIMER_EN);
2614 pwrap_writel(wrp, 0x1, PWRAP_TIMER_EN);
2616 pwrap_writel(wrp, wrp->master->int_en_all, PWRAP_INT_EN);
2621 if (HAS_CAP(wrp->master->caps, PWRAP_CAP_INT1_EN))
2622 pwrap_writel(wrp, wrp->master->int1_en_all, PWRAP_INT1_EN);
2630 ret = devm_request_irq(wrp->dev, irq, pwrap_interrupt,
2632 "mt-pmic-pwrap", wrp);
2636 wrp->regmap = devm_regmap_init(wrp->dev, NULL, wrp, wrp->slave->regops->regmap);
2637 if (IS_ERR(wrp->regmap)) {
2638 ret = PTR_ERR(wrp->regmap);
2642 ret = of_platform_populate(np, NULL, NULL, wrp->dev);
2644 dev_dbg(wrp->dev, "failed to create child devices at %pOF\n",
2652 clk_disable_unprepare(wrp->clk_tmr);
2654 clk_disable_unprepare(wrp->clk_sys);
2656 clk_disable_unprepare(wrp->clk_wrap);
2658 clk_disable_unprepare(wrp->clk_spi);