Lines Matching defs:queue
29 void qmgr_put_entry(unsigned int queue, u32 val)
32 BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
35 qmgr_queue_descs[queue], queue, val);
37 __raw_writel(val, &qmgr_regs->acc[queue][0]);
40 u32 qmgr_get_entry(unsigned int queue)
43 val = __raw_readl(&qmgr_regs->acc[queue][0]);
45 BUG_ON(!qmgr_queue_descs[queue]); /* not yet requested */
48 qmgr_queue_descs[queue], queue, val);
53 static int __qmgr_get_stat1(unsigned int queue)
55 return (__raw_readl(&qmgr_regs->stat1[queue >> 3])
56 >> ((queue & 7) << 2)) & 0xF;
59 static int __qmgr_get_stat2(unsigned int queue)
61 BUG_ON(queue >= HALF_QUEUES);
62 return (__raw_readl(&qmgr_regs->stat2[queue >> 4])
63 >> ((queue & 0xF) << 1)) & 0x3;
67 * qmgr_stat_empty() - checks if a hardware queue is empty
68 * @queue: queue number
70 * Returns non-zero value if the queue is empty.
72 int qmgr_stat_empty(unsigned int queue)
74 BUG_ON(queue >= HALF_QUEUES);
75 return __qmgr_get_stat1(queue) & QUEUE_STAT1_EMPTY;
79 * qmgr_stat_below_low_watermark() - checks if a queue is below low watermark
80 * @queue: queue number
82 * Returns non-zero value if the queue is below low watermark.
84 int qmgr_stat_below_low_watermark(unsigned int queue)
86 if (queue >= HALF_QUEUES)
88 (queue - HALF_QUEUES)) & 0x01;
89 return __qmgr_get_stat1(queue) & QUEUE_STAT1_NEARLY_EMPTY;
93 * qmgr_stat_full() - checks if a hardware queue is full
94 * @queue: queue number
96 * Returns non-zero value if the queue is full.
98 int qmgr_stat_full(unsigned int queue)
100 if (queue >= HALF_QUEUES)
102 (queue - HALF_QUEUES)) & 0x01;
103 return __qmgr_get_stat1(queue) & QUEUE_STAT1_FULL;
107 * qmgr_stat_overflow() - checks if a hardware queue experienced overflow
108 * @queue: queue number
110 * Returns non-zero value if the queue experienced overflow.
112 int qmgr_stat_overflow(unsigned int queue)
114 return __qmgr_get_stat2(queue) & QUEUE_STAT2_OVERFLOW;
117 void qmgr_set_irq(unsigned int queue, int src,
123 if (queue < HALF_QUEUES) {
127 reg = &qmgr_regs->irqsrc[queue >> 3]; /* 8 queues per u32 */
128 bit = (queue % 8) * 4; /* 3 bits + 1 reserved bit per queue */
135 irq_handlers[queue] = handler;
136 irq_pdevs[queue] = pdev;
151 i = __fls(en_bitmap); /* number of the last "low" queue */
177 i = __fls(req_bitmap); /* number of the last "high" queue */
196 i = __fls(req_bitmap); /* number of the last queue */
205 void qmgr_enable_irq(unsigned int queue)
208 int half = queue / 32;
209 u32 mask = 1 << (queue & (HALF_QUEUES - 1));
217 void qmgr_disable_irq(unsigned int queue)
220 int half = queue / 32;
221 u32 mask = 1 << (queue & (HALF_QUEUES - 1));
239 int qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
244 int __qmgr_request_queue(unsigned int queue, unsigned int len /* dwords */,
252 BUG_ON(queue >= QUEUES);
287 if (__raw_readl(&qmgr_regs->sram[queue])) {
303 " queue %i\n", queue);
313 __raw_writel(cfg | (addr << 14), &qmgr_regs->sram[queue]);
315 snprintf(qmgr_queue_descs[queue], sizeof(qmgr_queue_descs[0]),
317 printk(KERN_DEBUG "qmgr: requested queue %s(%i) addr = 0x%02X\n",
318 qmgr_queue_descs[queue], queue, addr);
329 void qmgr_release_queue(unsigned int queue)
333 BUG_ON(queue >= QUEUES); /* not in valid range */
336 cfg = __raw_readl(&qmgr_regs->sram[queue]);
354 printk(KERN_DEBUG "qmgr: releasing queue %s(%i)\n",
355 qmgr_queue_descs[queue], queue);
356 qmgr_queue_descs[queue][0] = '\x0';
359 while ((addr = qmgr_get_entry(queue)))
360 printk(KERN_ERR "qmgr: released queue %i not empty: 0x%08X\n",
361 queue, addr);
363 __raw_writel(0, &qmgr_regs->sram[queue]);
369 irq_handlers[queue] = NULL; /* catch IRQ bugs */
454 .compatible = "intel,ixp4xx-ahb-queue-manager",