Lines Matching refs:val
177 u8 bursts, val;
181 val = of_getintprop_default(dma_dp, "burst-sizes", 0xff);
182 if (val != 0xff)
183 bursts &= val;
185 val = of_getintprop_default(dma_dp->parent, "burst-sizes", 0xff);
186 if (val != 0xff)
187 bursts &= val;
205 static void sbus_esp_write8(struct esp *esp, u8 val, unsigned long reg)
207 sbus_writeb(val, esp->regs + (reg * 4UL));
227 u32 val;
240 val = dma_read32(DMA_CSR);
241 dma_write32(val | DMA_RST_SCSI, DMA_CSR);
242 dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
284 val = dma_read32(DMA_CSR);
285 dma_write32(val | DMA_3CLKS, DMA_CSR);
290 val = dma_read32(DMA_CSR);
291 val &= ~DMA_3CLKS;
292 val |= DMA_2CLKS;
294 val &= ~DMA_BRST_SZ;
295 val |= DMA_BRST32;
297 dma_write32(val, DMA_CSR);
301 val = dma_read32(DMA_CSR);
302 val |= DMA_ADD_ENABLE;
303 val &= ~DMA_BCNT_ENAB;
305 val |= DMA_ESC_BURST;
307 val &= ~(DMA_ESC_BURST);
309 dma_write32(val, DMA_CSR);
317 val = dma_read32(DMA_CSR);
318 dma_write32(val | DMA_INT_ENAB, DMA_CSR);
365 u32 val;
369 while ((val = dma_read32(DMA_CSR)) & DMA_PEND_READ) {
378 val &= ~(DMA_ENABLE | DMA_ST_WRITE | DMA_BCNT_ENAB);
379 val |= DMA_FIFO_INV;
380 dma_write32(val, DMA_CSR);
381 val &= ~DMA_FIFO_INV;
382 dma_write32(val, DMA_CSR);
499 u32 val = dma_read32(DMA_CSR);
501 dma_write32(val & ~DMA_RST_SCSI, DMA_CSR);
559 u32 val;
564 val = dma_read32(DMA_CSR);
565 dma_write32(val & ~DMA_INT_ENAB, DMA_CSR);