Lines Matching defs:dregs
159 static volatile struct sun3_dma_regs *dregs;
173 dregs->udc_addr = UDC_CSR;
175 ret = dregs->udc_data;
183 dregs->udc_addr = reg;
185 dregs->udc_data = val;
196 unsigned short csr = dregs->csr;
200 dregs->csr &= ~CSR_DMA_ENABLE;
238 dregs->fifo_count = 0;
242 dregs->csr &= ~CSR_FIFO;
243 dregs->csr |= CSR_FIFO;
248 dregs->csr |= CSR_SEND;
250 dregs->csr &= ~CSR_SEND;
253 dregs->csr |= CSR_PACK_ENABLE;
255 dregs->dma_addr_hi = ((unsigned long)addr >> 16);
256 dregs->dma_addr_lo = ((unsigned long)addr & 0xffff);
258 dregs->dma_count_hi = 0;
259 dregs->dma_count_lo = 0;
260 dregs->fifo_count_hi = 0;
261 dregs->fifo_count = 0;
264 dregs->fifo_count = count;
269 dregs->csr &= ~CSR_FIFO;
270 dregs->csr |= CSR_FIFO;
272 if(dregs->fifo_count != count) {
275 dregs->fifo_count, (unsigned int) count);
350 csr = dregs->csr;
352 dregs->dma_count_hi = (sun3_dma_orig_count >> 16);
353 dregs->dma_count_lo = (sun3_dma_orig_count & 0xffff);
355 dregs->fifo_count_hi = (sun3_dma_orig_count >> 16);
356 dregs->fifo_count = (sun3_dma_orig_count & 0xffff);
359 * dregs->csr |= CSR_DMA_ENABLE;
379 dregs->csr &= ~CSR_DMA_ENABLE;
381 fifo = dregs->fifo_count;
389 if ((!write_flag) && (dregs->csr & CSR_LEFT)) {
397 switch (dregs->csr & CSR_LEFT) {
399 *vaddr = (dregs->bpack_lo & 0xff00) >> 8;
404 *vaddr = (dregs->bpack_hi & 0x00ff);
409 *vaddr = (dregs->bpack_hi & 0xff00) >> 8;
419 if(dregs->csr & CSR_FIFO_EMPTY)
430 dregs->udc_addr = 0x32;
432 count = 2 * dregs->udc_data;
435 fifo = dregs->fifo_count;
443 data = dregs->fifo_data;
457 dregs->dma_addr_hi = 0;
458 dregs->dma_addr_lo = 0;
459 dregs->dma_count_hi = 0;
460 dregs->dma_count_lo = 0;
462 dregs->fifo_count = 0;
463 dregs->fifo_count_hi = 0;
465 dregs->csr &= ~CSR_SEND;
466 /* dregs->csr |= CSR_DMA_ENABLE; */
469 dregs->fifo_count = 0;
470 dregs->csr &= ~CSR_SEND;
473 dregs->csr &= ~CSR_FIFO;
474 dregs->csr |= CSR_FIFO;
544 dregs = (struct sun3_dma_regs *)(ioaddr + 8);
546 if (sun3_map_test((unsigned long)dregs, &x)) {
549 oldcsr = dregs->csr;
550 dregs->csr = 0;
552 if (dregs->csr == 0x1400)
555 dregs->csr = oldcsr;
570 dregs = (struct sun3_dma_regs *)(ioaddr + 8);
605 dregs->csr = 0;
607 dregs->csr = CSR_SCSI | CSR_FIFO | CSR_INTR;
609 dregs->fifo_count = 0;
611 dregs->fifo_count_hi = 0;
612 dregs->dma_addr_hi = 0;
613 dregs->dma_addr_lo = 0;
614 dregs->dma_count_hi = 0;
615 dregs->dma_count_lo = 0;
617 dregs->ivect = VME_DATA24 | (instance->irq & 0xff);