Lines Matching defs:qbase
85 int qbase = priv->qbase;
88 x = inb(qbase + 0xd);
90 outb(3, qbase + 3); /* reset SCSI */
91 outb(2, qbase + 3); /* reset chip */
104 int qbase = priv->qbase;
110 if (reqlen >= 128 && (inb(qbase + 8) & 2)) { /* full */
111 insl(qbase + 4, request, 32);
116 if ((j = inb(qbase + 8)) & 4)
118 insl(qbase + 4, request, 21);
122 if (reqlen >= 44 && (inb(qbase + 8) & 8)) { /* 1/3 */
123 insl(qbase + 4, request, 11);
135 while (reqlen && !((j = inb(qbase + 8)) & 0x10))
137 *request++ = inb(qbase + 4);
141 j = inb(qbase + 8);
147 if (reqlen >= 128 && inb(qbase + 8) & 0x10) { /* empty */
148 outsl(qbase + 4, request, 32);
153 if (!((j = inb(qbase + 8)) & 8)) {
154 outsl(qbase + 4, request, 21);
158 if (reqlen >= 40 && !(inb(qbase + 8) & 4)) { /* 2/3 */
159 outsl(qbase + 4, request, 10);
169 while (reqlen && !((j = inb(qbase + 8)) & 2))
171 outb(*request++, qbase + 4);
175 j = inb(qbase + 8);
179 return inb(qbase + 8) & 0xc0;
189 int qbase = priv->qbase;
195 !((k = inb(qbase + 4)) & 0xe0)) {
220 int qbase = priv->qbase;
229 inb(qbase + 5); /* clear interrupts */
230 if (inb(qbase + 5)) /* if still interrupting */
231 outb(2, qbase + 3); /* reset chip */
232 else if (inb(qbase + 7) & 0x1f)
233 outb(1, qbase + 3); /* clear fifo */
234 while (inb(qbase + 5)); /* clear ints */
236 outb(1, qbase + 8); /* set for PIO pseudo DMA */
237 outb(0, qbase + 0xb); /* disable ints */
238 inb(qbase + 8); /* clear int bits */
240 outb(0x40, qbase + 0xb); /* enable features */
243 outb(qlcfgc, qbase + 0xc);
245 outb(0x40 | qlcfg8 | priv->qinitid, qbase + 8);
246 outb(qlcfg7, qbase + 7);
247 outb(qlcfg6, qbase + 6);
248 outb(qlcfg5, qbase + 5); /* select timer */
249 outb(qlcfg9 & 7, qbase + 9); /* prescaler */
250 /* outb(0x99, qbase + 5); */
251 outb(scmd_id(cmd), qbase + 4);
254 outb(cmd->cmnd[i], qbase + 2);
257 outb(0x41, qbase + 3); /* select and send command */
274 int qbase = priv->qbase;
278 j = inb(qbase + 6);
279 i = inb(qbase + 5);
284 i |= inb(qbase + 5); /* the 0x10 bit can be set after the 0x08 */
291 j &= 7; /* j = inb( qbase + 7 ) >> 5; */
300 j, i, inb(qbase + 7) & 0x1f);
306 if (inb(qbase + 7) & 0x1f) /* if some bytes in fifo */
307 outb(1, qbase + 3); /* clear fifo */
311 if (reqlen && !((phase = inb(qbase + 4)) & 6)) { /* data phase */
314 outb(reqlen, qbase); /* low-mid xfer cnt */
315 outb(reqlen >> 8, qbase + 1); /* low-mid xfer cnt */
316 outb(reqlen >> 16, qbase + 0xe); /* high xfer cnt */
317 outb(0x90, qbase + 3); /* command do xfer */
342 k = inb(qbase + 5); /* should be 0x10, bus service */
352 !(inb(qbase + 4) & 6))
362 while (inb(qbase + 5))
371 outb(0x11, qbase + 3); /* get status and message */
376 i = inb(qbase + 5); /* get chip irq stat */
377 j = inb(qbase + 7) & 0x1f; /* and bytes rec'd */
378 status = inb(qbase + 2);
379 message = inb(qbase + 2);
389 outb(0x12, qbase + 3); /* done, disconnect */
400 i = inb(qbase + 5); /* should be bus service */
404 i |= inb(qbase + 5);
430 int qbase = priv->qbase;
433 if (!(inb(qbase + 4) & 0x80)) /* false alarm? */
439 while (i-- && inb(qbase + 5)); /* maybe also ql_zap() */
560 int qlogicfas408_get_chip_type(int qbase, int int_type)
563 return inb(qbase + 0xe) & 0xf8;
570 void qlogicfas408_setup(int qbase, int id, int int_type)
572 outb(1, qbase + 8); /* set for PIO pseudo DMA */
574 outb(0x40 | qlcfg8 | id, qbase + 8); /* (ini) bus id, disable scsi rst */
575 outb(qlcfg5, qbase + 5); /* select timer */
576 outb(qlcfg9, qbase + 9); /* prescaler */
579 outb(3, qbase + 3);
583 while (inb(qbase + 0xf) & 4)
594 int qlogicfas408_detect(int qbase, int int_type)
597 return (((inb(qbase + 0xe) ^ inb(qbase + 0xe)) == 7) &&
598 ((inb(qbase + 0xe) ^ inb(qbase + 0xe)) == 7));
607 int qbase = priv->qbase;
611 outb(0, qbase + 0xb); /* disable ints */