Lines Matching defs:temp
1289 uint32_t temp;
1349 temp = off8 + (i << shift_amount);
1350 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1351 temp = 0;
1352 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1353 temp = word[i * scale] & 0xffffffff;
1354 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1355 temp = (word[i * scale] >> 32) & 0xffffffff;
1356 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1357 temp = word[i*scale + 1] & 0xffffffff;
1359 MIU_TEST_AGT_WRDATA_UPPER_LO, temp);
1360 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1362 MIU_TEST_AGT_WRDATA_UPPER_HI, temp);
1364 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1365 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1366 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1367 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1370 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1371 if ((temp & MIU_TA_CTL_BUSY) == 0)
1426 uint32_t temp;
1451 temp = off8 + (i << shift_amount);
1452 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1453 temp = 0;
1454 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1455 temp = MIU_TA_CTL_ENABLE;
1456 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1457 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1458 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1461 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1462 if ((temp & MIU_TA_CTL_BUSY) == 0)
1476 temp = qla82xx_rd_32(ha,
1478 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
3274 uint32_t temp, temp_state, temp_val;
3277 temp = qla82xx_rd_32(ha, CRB_TEMP_STATE);
3278 temp_state = qla82xx_get_temp_state(temp);
3279 temp_val = qla82xx_get_temp_val(temp);
3298 uint32_t temp;
3300 temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE);
3301 return qla82xx_get_temp_val(temp);
4304 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",