Lines Matching defs:r_value
3793 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3803 r_value = rd_reg_dword(r_addr + ha->nx_pcibase);
3804 *data_ptr++ = cpu_to_le32(r_value);
3815 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
3828 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3830 *data_ptr++ = cpu_to_le32(r_value);
3841 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3851 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3853 *data_ptr++ = cpu_to_le32(r_value);
3865 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3908 r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3909 *data_ptr++ = cpu_to_le32(r_value);
3924 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3944 r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3945 *data_ptr++ = cpu_to_le32(r_value);
3959 uint32_t r_stride, r_value, r_cnt, qid = 0;
3974 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3975 *data_ptr++ = cpu_to_le32(r_value);
3988 uint32_t r_addr, r_value;
4000 r_value = qla82xx_md_rw_32(ha,
4003 *data_ptr++ = cpu_to_le32(r_value);
4014 uint32_t r_addr, r_value, r_data;
4045 r_value = 0;
4046 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1);
4047 r_value = MIU_TA_CTL_ENABLE;
4048 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4049 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
4050 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4053 r_value = qla82xx_md_rw_32(ha,
4055 if ((r_value & MIU_TA_CTL_BUSY) == 0)