Lines Matching refs:ctrl_status
2859 ha->pci_attr = rd_reg_word(®->ctrl_status);
2910 wrt_reg_word(®->ctrl_status, 0x20);
2911 rd_reg_word(®->ctrl_status);
2920 wrt_reg_word(®->ctrl_status, 0x0);
2921 rd_reg_word(®->ctrl_status);
2941 ha->pci_attr = rd_reg_word(®->ctrl_status);
2985 ha->pci_attr = rd_reg_dword(®->ctrl_status);
3103 wrt_reg_word(®->ctrl_status, 0x20);
3104 rd_reg_word(®->ctrl_status); /* PCI Posting. */
3117 wrt_reg_word(®->ctrl_status, 0x10);
3118 rd_reg_word(®->ctrl_status); /* PCI Posting. */
3136 wrt_reg_word(®->ctrl_status, 0);
3137 rd_reg_word(®->ctrl_status); /* PCI Posting. */
3152 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET);
3163 if ((rd_reg_word(®->ctrl_status) &
3286 wrt_reg_dword(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
3288 if ((rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
3294 if (!(rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE))
3300 rd_reg_dword(®->ctrl_status),
3301 (rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE));
3303 wrt_reg_dword(®->ctrl_status,
3329 rd_reg_dword(®->ctrl_status);
3332 if ((rd_reg_dword(®->ctrl_status) &
3338 if (!(rd_reg_dword(®->ctrl_status) & CSRX_ISP_SOFT_RESET))
3344 rd_reg_dword(®->ctrl_status));
3543 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET);
3550 data = qla2x00_debounce_register(®->ctrl_status);
3553 data = rd_reg_word(®->ctrl_status);
5215 if ((rd_reg_word(®->ctrl_status) >> 14) == 1)