Lines Matching refs:mb
1108 uint16_t mb[MAILBOX_REGISTER_COUNT];
1117 mb[0] = MBC_SET_TARGET_PARAMETERS;
1118 mb[1] = (uint16_t)((bus ? target | BIT_7 : target) << 8);
1119 mb[2] = nv->bus[bus].target[target].parameter.renegotiate_on_error << 8;
1120 mb[2] |= nv->bus[bus].target[target].parameter.stop_queue_on_check << 9;
1121 mb[2] |= nv->bus[bus].target[target].parameter.auto_request_sense << 10;
1122 mb[2] |= nv->bus[bus].target[target].parameter.tag_queuing << 11;
1123 mb[2] |= nv->bus[bus].target[target].parameter.enable_sync << 12;
1124 mb[2] |= nv->bus[bus].target[target].parameter.enable_wide << 13;
1125 mb[2] |= nv->bus[bus].target[target].parameter.parity_checking << 14;
1126 mb[2] |= nv->bus[bus].target[target].parameter.disconnect_allowed << 15;
1129 mb[2] |= nv->bus[bus].target[target].ppr_1x160.flags.enable_ppr << 5;
1130 mb[3] = (nv->bus[bus].target[target].flags.flags1x160.sync_offset << 8);
1131 mb[6] = (nv->bus[bus].target[target].ppr_1x160.flags.ppr_options << 8) |
1135 mb[3] = (nv->bus[bus].target[target].flags.flags1x80.sync_offset << 8);
1137 mb[3] |= nv->bus[bus].target[target].sync_period;
1139 status = qla1280_mailbox_command(ha, mr, mb);
1143 mb[0] = MBC_SET_DEVICE_QUEUE;
1144 mb[1] = (uint16_t)((bus ? target | BIT_7 : target) << 8);
1145 mb[1] |= lun;
1146 mb[2] = nv->bus[bus].max_queue_depth;
1147 mb[3] = nv->bus[bus].target[target].execution_throttle;
1148 status |= qla1280_mailbox_command(ha, 0x0f, mb);
1545 uint16_t mb[MAILBOX_REGISTER_COUNT];
1625 mb[0] = MBC_MAILBOX_REGISTER_TEST;
1626 mb[1] = 0xAAAA;
1627 mb[2] = 0x5555;
1628 mb[3] = 0xAA55;
1629 mb[4] = 0x55AA;
1630 mb[5] = 0xA5A5;
1631 mb[6] = 0x5A5A;
1632 mb[7] = 0x2525;
1634 status = qla1280_mailbox_command(ha, 0xff, mb);
1638 if (mb[1] != 0xAAAA || mb[2] != 0x5555 || mb[3] != 0xAA55 ||
1639 mb[4] != 0x55AA || mb[5] != 0xA5A5 || mb[6] != 0x5A5A ||
1640 mb[7] != 0x2525) {
1660 uint16_t mb[MAILBOX_REGISTER_COUNT], i;
1676 mb[0] = MBC_WRITE_RAM_WORD;
1677 mb[1] = risc_address + i;
1678 mb[2] = __le16_to_cpu(fw_data[i]);
1680 err = qla1280_mailbox_command(ha, BIT_0 | BIT_1 | BIT_2, mb);
1709 uint16_t mb[MAILBOX_REGISTER_COUNT], cnt;
1750 mb[0] = LOAD_CMD;
1751 mb[1] = risc_address;
1752 mb[4] = cnt;
1753 mb[3] = ha->request_dma & 0xffff;
1754 mb[2] = (ha->request_dma >> 16) & 0xffff;
1755 mb[7] = upper_32_bits(ha->request_dma) & 0xffff;
1756 mb[6] = upper_32_bits(ha->request_dma) >> 16;
1758 __func__, mb[0],
1760 mb[6], mb[7], mb[2], mb[3]);
1761 err = qla1280_mailbox_command(ha, CMD_ARGS, mb);
1769 mb[0] = DUMP_CMD;
1770 mb[1] = risc_address;
1771 mb[4] = cnt;
1772 mb[3] = p_tbuf & 0xffff;
1773 mb[2] = (p_tbuf >> 16) & 0xffff;
1774 mb[7] = upper_32_bits(p_tbuf) & 0xffff;
1775 mb[6] = upper_32_bits(p_tbuf) >> 16;
1777 err = qla1280_mailbox_command(ha, CMD_ARGS, mb);
1812 uint16_t mb[MAILBOX_REGISTER_COUNT];
1819 mb[0] = MBC_VERIFY_CHECKSUM;
1820 /* mb[1] = ql12_risc_code_addr01; */
1821 mb[1] = ha->fwstart;
1822 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
1830 mb[0] = MBC_EXECUTE_FIRMWARE;
1831 mb[1] = ha->fwstart;
1832 err = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
1877 uint16_t mb[MAILBOX_REGISTER_COUNT];
1890 /* mb[0] = MBC_INIT_REQUEST_QUEUE; */
1891 mb[0] = MBC_INIT_REQUEST_QUEUE_A64;
1892 mb[1] = REQUEST_ENTRY_CNT;
1893 mb[3] = ha->request_dma & 0xffff;
1894 mb[2] = (ha->request_dma >> 16) & 0xffff;
1895 mb[4] = 0;
1896 mb[7] = upper_32_bits(ha->request_dma) & 0xffff;
1897 mb[6] = upper_32_bits(ha->request_dma) >> 16;
1900 &mb[0]))) {
1904 /* mb[0] = MBC_INIT_RESPONSE_QUEUE; */
1905 mb[0] = MBC_INIT_RESPONSE_QUEUE_A64;
1906 mb[1] = RESPONSE_ENTRY_CNT;
1907 mb[3] = ha->response_dma & 0xffff;
1908 mb[2] = (ha->response_dma >> 16) & 0xffff;
1909 mb[5] = 0;
1910 mb[7] = upper_32_bits(ha->response_dma) & 0xffff;
1911 mb[6] = upper_32_bits(ha->response_dma) >> 16;
1914 &mb[0]);
2063 uint16_t mb[MAILBOX_REGISTER_COUNT];
2068 mb[0] = MBC_SET_TARGET_PARAMETERS;
2069 mb[1] = (uint16_t)((bus ? target | BIT_7 : target) << 8);
2076 mb[2] = (TP_RENEGOTIATE | TP_AUTO_REQUEST_SENSE | TP_TAGGED_QUEUE
2080 mb[3] = nv->bus[bus].target[target].flags.flags1x160.sync_offset << 8;
2082 mb[3] = nv->bus[bus].target[target].flags.flags1x80.sync_offset << 8;
2083 mb[3] |= nv->bus[bus].target[target].sync_period;
2084 status = qla1280_mailbox_command(ha, 0x0f, mb);
2106 mb[0] = MBC_SET_DEVICE_QUEUE;
2107 mb[1] = (uint16_t)((bus ? target | BIT_7 : target) << 8);
2108 mb[1] |= lun;
2109 mb[2] = nv->bus[bus].max_queue_depth;
2110 mb[3] = nv->bus[bus].target[target].execution_throttle;
2111 status |= qla1280_mailbox_command(ha, 0x0f, mb);
2121 uint16_t mb[MAILBOX_REGISTER_COUNT];
2130 mb[0] = MBC_SET_INITIATOR_ID;
2131 mb[1] = bus ? ha->bus_settings[bus].id | BIT_7 :
2133 status = qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
2155 uint16_t mb[MAILBOX_REGISTER_COUNT];
2216 mb[0] = MBC_SET_SYSTEM_PARAMETER;
2217 mb[1] = nv->isp_parameter;
2218 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, &mb[0]);
2222 mb[0] = MBC_SET_CLOCK_RATE;
2223 mb[1] = 40;
2224 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
2228 mb[0] = MBC_SET_FIRMWARE_FEATURES;
2229 mb[1] = nv->firmware_feature.f.enable_fast_posting;
2230 mb[1] |= nv->firmware_feature.f.report_lvd_bus_transition << 1;
2231 mb[1] |= nv->firmware_feature.f.disable_synchronous_backoff << 5;
2232 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
2235 mb[0] = MBC_SET_RETRY_COUNT;
2236 mb[1] = nv->bus[0].retry_count;
2237 mb[2] = nv->bus[0].retry_delay;
2238 mb[6] = nv->bus[1].retry_count;
2239 mb[7] = nv->bus[1].retry_delay;
2241 BIT_1 | BIT_0, &mb[0]);
2244 mb[0] = MBC_SET_ASYNC_DATA_SETUP;
2245 mb[1] = nv->bus[0].config_2.async_data_setup_time;
2246 mb[2] = nv->bus[1].config_2.async_data_setup_time;
2247 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
2250 mb[0] = MBC_SET_ACTIVE_NEGATION;
2251 mb[1] = 0;
2253 mb[1] |= BIT_5;
2255 mb[1] |= BIT_4;
2256 mb[2] = 0;
2258 mb[2] |= BIT_5;
2260 mb[2] |= BIT_4;
2261 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb);
2263 mb[0] = MBC_SET_DATA_OVERRUN_RECOVERY;
2264 mb[1] = 2; /* Reset SCSI bus and return all outstanding IO */
2265 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
2268 mb[0] = MBC_SET_PCI_CONTROL;
2269 mb[1] = BIT_1; /* Data DMA Channel Burst Enable */
2270 mb[2] = BIT_1; /* Command DMA Channel Burst Enable */
2271 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb);
2273 mb[0] = MBC_SET_TAG_AGE_LIMIT;
2274 mb[1] = 8;
2275 status |= qla1280_mailbox_command(ha, BIT_1 | BIT_0, mb);
2278 mb[0] = MBC_SET_SELECTION_TIMEOUT;
2279 mb[1] = nv->bus[0].selection_timeout;
2280 mb[2] = nv->bus[1].selection_timeout;
2281 status |= qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, mb);
2402 * mb = data pointer for mailbox registers.
2405 * mb[MAILBOX_REGISTER_COUNT] = returned mailbox data.
2411 qla1280_mailbox_command(struct scsi_qla_host *ha, uint8_t mr, uint16_t *mb)
2433 iptr = mb;
2466 mb[0], ha->mailbox_out[0], RD_REG_WORD(®->istatus));
2477 optr = mb;
2487 "0x%x ****\n", mb[0]);
2539 uint16_t mb[MAILBOX_REGISTER_COUNT];
2550 mb[0] = MBC_BUS_RESET;
2551 mb[1] = reset_delay;
2552 mb[2] = (uint16_t) bus;
2553 status = qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
2599 uint16_t mb[MAILBOX_REGISTER_COUNT];
2604 mb[0] = MBC_ABORT_TARGET;
2605 mb[1] = (bus ? (target | BIT_7) : target) << 8;
2606 mb[2] = 1;
2607 status = qla1280_mailbox_command(ha, BIT_2 | BIT_1 | BIT_0, &mb[0]);
2633 uint16_t mb[MAILBOX_REGISTER_COUNT];
2645 mb[0] = MBC_ABORT_COMMAND;
2646 mb[1] = (bus ? target | BIT_7 : target) << 8 | lun;
2647 mb[2] = handle >> 16;
2648 mb[3] = handle & 0xffff;
2649 status = qla1280_mailbox_command(ha, 0x0f, &mb[0]);
3882 uint16_t mb[MAILBOX_REGISTER_COUNT];
3890 mb[0] = MBC_GET_TARGET_PARAMETERS;
3891 mb[1] = (uint16_t) (bus ? target | BIT_7 : target);
3892 mb[1] <<= 8;
3894 &mb[0]);
3898 if (mb[3] != 0) {
3900 (mb[3] & 0xff), (mb[3] >> 8));
3901 if (mb[2] & BIT_13)
3903 if ((mb[2] & BIT_5) && ((mb[6] >> 8) & 0xff) >= 2)