Lines Matching refs:pm80xx_tbl
521 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature =
523 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev =
525 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev =
527 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_out_io =
529 pm8001_ha->main_cfg_tbl.pm80xx_tbl.max_sgl =
531 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ctrl_cap_flag =
533 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset =
535 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset =
537 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset =
541 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset0 =
543 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length0 =
545 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_offset1 =
547 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_dump_length1 =
551 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping =
555 pm8001_ha->main_cfg_tbl.pm80xx_tbl.analog_setup_table_offset =
558 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset =
560 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset =
563 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer =
566 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version =
568 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version =
573 pm8001_ha->main_cfg_tbl.pm80xx_tbl.signature,
574 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interface_rev,
575 pm8001_ha->main_cfg_tbl.pm80xx_tbl.firmware_rev);
579 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gst_offset,
580 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_queue_offset,
581 pm8001_ha->main_cfg_tbl.pm80xx_tbl.outbound_queue_offset,
582 pm8001_ha->main_cfg_tbl.pm80xx_tbl.int_vec_table_offset,
583 pm8001_ha->main_cfg_tbl.pm80xx_tbl.phy_attr_table_offset);
587 pm8001_ha->main_cfg_tbl.pm80xx_tbl.ila_version,
588 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inc_fw_version);
598 pm8001_ha->gs_tbl.pm80xx_tbl.gst_len_mpistate =
600 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state0 =
602 pm8001_ha->gs_tbl.pm80xx_tbl.iq_freeze_state1 =
604 pm8001_ha->gs_tbl.pm80xx_tbl.msgu_tcnt =
606 pm8001_ha->gs_tbl.pm80xx_tbl.iop_tcnt =
608 pm8001_ha->gs_tbl.pm80xx_tbl.gpio_input_val =
610 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[0] =
612 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[1] =
614 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[2] =
616 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[3] =
618 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[4] =
620 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[5] =
622 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[6] =
624 pm8001_ha->gs_tbl.pm80xx_tbl.recover_err_info[7] =
753 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr =
755 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr =
757 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size =
759 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity = 0x01;
760 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr =
762 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr =
764 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size =
766 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity = 0x01;
767 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt = 0x01;
771 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
774 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump = (0x1 << 16);
852 pm8001_ha->main_cfg_tbl.pm80xx_tbl.inbound_q_nppd_hppd);
854 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_event_log_addr);
856 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_event_log_addr);
858 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_size);
860 pm8001_ha->main_cfg_tbl.pm80xx_tbl.event_log_severity);
862 pm8001_ha->main_cfg_tbl.pm80xx_tbl.upper_pcs_event_log_addr);
864 pm8001_ha->main_cfg_tbl.pm80xx_tbl.lower_pcs_event_log_addr);
866 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_size);
868 pm8001_ha->main_cfg_tbl.pm80xx_tbl.pcs_event_log_severity);
870 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt |=
873 pm8001_ha->main_cfg_tbl.pm80xx_tbl.fatal_err_interrupt);
879 pm8001_ha->main_cfg_tbl.pm80xx_tbl.crc_core_dump);
882 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping &= 0xCFFFFFFF;
884 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping |= 0x20000000;
886 pm8001_ha->main_cfg_tbl.pm80xx_tbl.gpio_led_mapping);
892 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
894 pm8001_ha->main_cfg_tbl.pm80xx_tbl.interrupt_reassertion_delay);
896 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &= 0xffff0000;
897 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
900 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer &=
902 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer |=
906 pm8001_ha->main_cfg_tbl.pm80xx_tbl.port_recovery_timer);
4030 * pm8001_ha->max_q_num - 1 through pm8001_ha->main_cfg_tbl.pm80xx_tbl.