Lines Matching refs:regVal
393 u32 regVal;
402 regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
403 } while ((regVal != shiftValue) && time_before(jiffies, start));
405 if (regVal != shiftValue) {
408 regVal);
766 u32 regVal, regVal1, regVal2;
772 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
774 if (regVal == SCRATCH_PAD2_FWRDY_RST) {
792 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
794 if (regVal != SCRATCH_PAD2_FWRDY_RST) {
821 u32 regVal, toggleVal;
843 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
845 regVal);
854 regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
856 regVal);
859 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
861 regVal);
864 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
866 regVal);
867 pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
869 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
871 regVal);
874 regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
875 pm8001_dbg(pm8001_ha, INIT, "PCIE - Error Interrupt = 0x%x\n", regVal);
876 pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
879 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
881 toggleVal = regVal ^ SCRATCH_PAD1_RST;
900 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
909 regVal &= ~(0x00003b00);
911 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
955 regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
957 regVal);
959 regVal &= 0xFFFFFFFC;
960 pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
970 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
972 regVal);
973 regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
974 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
977 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
979 regVal);
980 regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
981 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
987 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
990 regVal);
991 regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
992 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1008 regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
1017 regVal |= (GSM_CONFIG_RESET_VALUE);
1018 pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
1023 regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
1027 regVal);
1032 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
1038 regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
1052 regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1053 regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1054 pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1065 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1067 } while ((regVal != toggleVal) && (--max_wait_count));
1070 regVal = pm8001_cr32(pm8001_ha, 0,
1073 toggleVal, regVal);
1098 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1102 regVal);
1103 regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1107 regVal);
1130 u32 regVal;
1134 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1135 regVal &= ~(SPC_REG_RESET_DEVICE);
1136 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1142 regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1143 regVal |= SPC_REG_RESET_DEVICE;
1144 pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);