Lines Matching defs:NSP32_DEBUG_INTR
299 #define NSP32_DEBUG_INTR BIT(3)
435 nsp32_dbg(NSP32_DEBUG_INTR, "timer=%d", time);
438 nsp32_dbg(NSP32_DEBUG_INTR, "timer set overflow");
1174 nsp32_dbg(NSP32_DEBUG_INTR,
1178 nsp32_dbg(NSP32_DEBUG_INTR,
1201 nsp32_dbg(NSP32_DEBUG_INTR, "timer stop");
1237 nsp32_dbg(NSP32_DEBUG_INTR,
1262 nsp32_dbg(NSP32_DEBUG_INTR, "MsgOut phase processed");
1274 nsp32_dbg(NSP32_DEBUG_INTR,
1278 nsp32_dbg(NSP32_DEBUG_INTR, "BMCNT=0x%lx",
1280 nsp32_dbg(NSP32_DEBUG_INTR, "addr=0x%lx",
1282 nsp32_dbg(NSP32_DEBUG_INTR, "SACK=0x%lx",
1284 nsp32_dbg(NSP32_DEBUG_INTR, "SSACK=0x%lx",
1343 nsp32_dbg(NSP32_DEBUG_INTR, "Command phase processed");
1355 nsp32_dbg(NSP32_DEBUG_INTR, "FIFO IRQ");
1359 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/write");
1366 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/read");
1373 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/status");
1379 nsp32_dbg(NSP32_DEBUG_INTR, "fifo/other phase");
1380 nsp32_dbg(NSP32_DEBUG_INTR, "irq_stat=0x%x trans_stat=0x%x",
1391 nsp32_dbg(NSP32_DEBUG_INTR, "phase change IRQ");
1395 nsp32_dbg(NSP32_DEBUG_INTR, "phase chg/msg in");
1410 nsp32_dbg(NSP32_DEBUG_INTR, "PCI IRQ occurred");
1425 nsp32_dbg(NSP32_DEBUG_INTR,
1437 nsp32_dbg(NSP32_DEBUG_INTR, "exit");