Lines Matching refs:base
165 void __iomem *base = cb->io_base;
172 cb->get_cmd_mbox(base);
808 void __iomem *base = cb->io_base;
849 /* These are the base addresses for the command memory mailbox array */
865 /* These are the base addresses for the status memory mailbox array */
888 status = mmio_init_fn(pdev, base, &mbox);
892 status = mmio_init_fn(pdev, base, &mbox);
2517 static inline void DAC960_LA_hw_mbox_new_cmd(void __iomem *base)
2519 writeb(DAC960_LA_IDB_HWMBOX_NEW_CMD, base + DAC960_LA_IDB_OFFSET);
2522 static inline void DAC960_LA_ack_hw_mbox_status(void __iomem *base)
2524 writeb(DAC960_LA_IDB_HWMBOX_ACK_STS, base + DAC960_LA_IDB_OFFSET);
2527 static inline void DAC960_LA_reset_ctrl(void __iomem *base)
2529 writeb(DAC960_LA_IDB_CTRL_RESET, base + DAC960_LA_IDB_OFFSET);
2532 static inline void DAC960_LA_mem_mbox_new_cmd(void __iomem *base)
2534 writeb(DAC960_LA_IDB_MMBOX_NEW_CMD, base + DAC960_LA_IDB_OFFSET);
2537 static inline bool DAC960_LA_hw_mbox_is_full(void __iomem *base)
2539 unsigned char idb = readb(base + DAC960_LA_IDB_OFFSET);
2544 static inline bool DAC960_LA_init_in_progress(void __iomem *base)
2546 unsigned char idb = readb(base + DAC960_LA_IDB_OFFSET);
2551 static inline void DAC960_LA_ack_hw_mbox_intr(void __iomem *base)
2553 writeb(DAC960_LA_ODB_HWMBOX_ACK_IRQ, base + DAC960_LA_ODB_OFFSET);
2556 static inline void DAC960_LA_ack_intr(void __iomem *base)
2559 base + DAC960_LA_ODB_OFFSET);
2562 static inline bool DAC960_LA_hw_mbox_status_available(void __iomem *base)
2564 unsigned char odb = readb(base + DAC960_LA_ODB_OFFSET);
2569 static inline void DAC960_LA_enable_intr(void __iomem *base)
2574 writeb(odb, base + DAC960_LA_IRQMASK_OFFSET);
2577 static inline void DAC960_LA_disable_intr(void __iomem *base)
2582 writeb(odb, base + DAC960_LA_IRQMASK_OFFSET);
2598 static inline void DAC960_LA_write_hw_mbox(void __iomem *base,
2601 writel(mbox->words[0], base + DAC960_LA_CMDOP_OFFSET);
2602 writel(mbox->words[1], base + DAC960_LA_MBOX4_OFFSET);
2603 writel(mbox->words[2], base + DAC960_LA_MBOX8_OFFSET);
2604 writeb(mbox->bytes[12], base + DAC960_LA_MBOX12_OFFSET);
2607 static inline unsigned short DAC960_LA_read_status(void __iomem *base)
2609 return readw(base + DAC960_LA_STS_OFFSET);
2613 DAC960_LA_read_error_status(void __iomem *base, unsigned char *error,
2616 unsigned char errsts = readb(base + DAC960_LA_ERRSTS_OFFSET);
2623 *param0 = readb(base + DAC960_LA_CMDOP_OFFSET);
2624 *param1 = readb(base + DAC960_LA_CMDID_OFFSET);
2625 writeb(0xFF, base + DAC960_LA_ERRSTS_OFFSET);
2630 DAC960_LA_mbox_init(struct pci_dev *pdev, void __iomem *base,
2637 if (!DAC960_LA_hw_mbox_is_full(base))
2642 if (DAC960_LA_hw_mbox_is_full(base)) {
2647 DAC960_LA_write_hw_mbox(base, mbox);
2648 DAC960_LA_hw_mbox_new_cmd(base);
2651 if (DAC960_LA_hw_mbox_status_available(base))
2656 if (!DAC960_LA_hw_mbox_status_available(base)) {
2660 status = DAC960_LA_read_status(base);
2661 DAC960_LA_ack_hw_mbox_intr(base);
2662 DAC960_LA_ack_hw_mbox_status(base);
2668 struct myrb_hba *cb, void __iomem *base)
2673 DAC960_LA_disable_intr(base);
2674 DAC960_LA_ack_hw_mbox_status(base);
2676 while (DAC960_LA_init_in_progress(base) &&
2678 if (DAC960_LA_read_error_status(base, &error,
2693 DAC960_LA_reset_ctrl(base);
2696 DAC960_LA_enable_intr(base);
2712 void __iomem *base = cb->io_base;
2717 DAC960_LA_ack_intr(base);
2764 static inline void DAC960_PG_hw_mbox_new_cmd(void __iomem *base)
2766 writel(DAC960_PG_IDB_HWMBOX_NEW_CMD, base + DAC960_PG_IDB_OFFSET);
2769 static inline void DAC960_PG_ack_hw_mbox_status(void __iomem *base)
2771 writel(DAC960_PG_IDB_HWMBOX_ACK_STS, base + DAC960_PG_IDB_OFFSET);
2774 static inline void DAC960_PG_reset_ctrl(void __iomem *base)
2776 writel(DAC960_PG_IDB_CTRL_RESET, base + DAC960_PG_IDB_OFFSET);
2779 static inline void DAC960_PG_mem_mbox_new_cmd(void __iomem *base)
2781 writel(DAC960_PG_IDB_MMBOX_NEW_CMD, base + DAC960_PG_IDB_OFFSET);
2784 static inline bool DAC960_PG_hw_mbox_is_full(void __iomem *base)
2786 unsigned char idb = readl(base + DAC960_PG_IDB_OFFSET);
2791 static inline bool DAC960_PG_init_in_progress(void __iomem *base)
2793 unsigned char idb = readl(base + DAC960_PG_IDB_OFFSET);
2798 static inline void DAC960_PG_ack_hw_mbox_intr(void __iomem *base)
2800 writel(DAC960_PG_ODB_HWMBOX_ACK_IRQ, base + DAC960_PG_ODB_OFFSET);
2803 static inline void DAC960_PG_ack_intr(void __iomem *base)
2806 base + DAC960_PG_ODB_OFFSET);
2809 static inline bool DAC960_PG_hw_mbox_status_available(void __iomem *base)
2811 unsigned char odb = readl(base + DAC960_PG_ODB_OFFSET);
2816 static inline void DAC960_PG_enable_intr(void __iomem *base)
2821 writel(imask, base + DAC960_PG_IRQMASK_OFFSET);
2824 static inline void DAC960_PG_disable_intr(void __iomem *base)
2828 writel(imask, base + DAC960_PG_IRQMASK_OFFSET);
2844 static inline void DAC960_PG_write_hw_mbox(void __iomem *base,
2847 writel(mbox->words[0], base + DAC960_PG_CMDOP_OFFSET);
2848 writel(mbox->words[1], base + DAC960_PG_MBOX4_OFFSET);
2849 writel(mbox->words[2], base + DAC960_PG_MBOX8_OFFSET);
2850 writeb(mbox->bytes[12], base + DAC960_PG_MBOX12_OFFSET);
2854 DAC960_PG_read_status(void __iomem *base)
2856 return readw(base + DAC960_PG_STS_OFFSET);
2860 DAC960_PG_read_error_status(void __iomem *base, unsigned char *error,
2863 unsigned char errsts = readb(base + DAC960_PG_ERRSTS_OFFSET);
2869 *param0 = readb(base + DAC960_PG_CMDOP_OFFSET);
2870 *param1 = readb(base + DAC960_PG_CMDID_OFFSET);
2871 writeb(0, base + DAC960_PG_ERRSTS_OFFSET);
2876 DAC960_PG_mbox_init(struct pci_dev *pdev, void __iomem *base,
2883 if (!DAC960_PG_hw_mbox_is_full(base))
2888 if (DAC960_PG_hw_mbox_is_full(base)) {
2893 DAC960_PG_write_hw_mbox(base, mbox);
2894 DAC960_PG_hw_mbox_new_cmd(base);
2898 if (DAC960_PG_hw_mbox_status_available(base))
2903 if (!DAC960_PG_hw_mbox_status_available(base)) {
2908 status = DAC960_PG_read_status(base);
2909 DAC960_PG_ack_hw_mbox_intr(base);
2910 DAC960_PG_ack_hw_mbox_status(base);
2916 struct myrb_hba *cb, void __iomem *base)
2921 DAC960_PG_disable_intr(base);
2922 DAC960_PG_ack_hw_mbox_status(base);
2924 while (DAC960_PG_init_in_progress(base) &&
2926 if (DAC960_PG_read_error_status(base, &error,
2941 DAC960_PG_reset_ctrl(base);
2944 DAC960_PG_enable_intr(base);
2960 void __iomem *base = cb->io_base;
2965 DAC960_PG_ack_intr(base);
3012 static inline void DAC960_PD_hw_mbox_new_cmd(void __iomem *base)
3014 writeb(DAC960_PD_IDB_HWMBOX_NEW_CMD, base + DAC960_PD_IDB_OFFSET);
3017 static inline void DAC960_PD_ack_hw_mbox_status(void __iomem *base)
3019 writeb(DAC960_PD_IDB_HWMBOX_ACK_STS, base + DAC960_PD_IDB_OFFSET);
3022 static inline void DAC960_PD_reset_ctrl(void __iomem *base)
3024 writeb(DAC960_PD_IDB_CTRL_RESET, base + DAC960_PD_IDB_OFFSET);
3027 static inline bool DAC960_PD_hw_mbox_is_full(void __iomem *base)
3029 unsigned char idb = readb(base + DAC960_PD_IDB_OFFSET);
3034 static inline bool DAC960_PD_init_in_progress(void __iomem *base)
3036 unsigned char idb = readb(base + DAC960_PD_IDB_OFFSET);
3041 static inline void DAC960_PD_ack_intr(void __iomem *base)
3043 writeb(DAC960_PD_ODB_HWMBOX_ACK_IRQ, base + DAC960_PD_ODB_OFFSET);
3046 static inline bool DAC960_PD_hw_mbox_status_available(void __iomem *base)
3048 unsigned char odb = readb(base + DAC960_PD_ODB_OFFSET);
3053 static inline void DAC960_PD_enable_intr(void __iomem *base)
3055 writeb(DAC960_PD_IRQMASK_ENABLE_IRQ, base + DAC960_PD_IRQEN_OFFSET);
3058 static inline void DAC960_PD_disable_intr(void __iomem *base)
3060 writeb(0, base + DAC960_PD_IRQEN_OFFSET);
3063 static inline void DAC960_PD_write_cmd_mbox(void __iomem *base,
3066 writel(mbox->words[0], base + DAC960_PD_CMDOP_OFFSET);
3067 writel(mbox->words[1], base + DAC960_PD_MBOX4_OFFSET);
3068 writel(mbox->words[2], base + DAC960_PD_MBOX8_OFFSET);
3069 writeb(mbox->bytes[12], base + DAC960_PD_MBOX12_OFFSET);
3073 DAC960_PD_read_status_cmd_ident(void __iomem *base)
3075 return readb(base + DAC960_PD_STSID_OFFSET);
3079 DAC960_PD_read_status(void __iomem *base)
3081 return readw(base + DAC960_PD_STS_OFFSET);
3085 DAC960_PD_read_error_status(void __iomem *base, unsigned char *error,
3088 unsigned char errsts = readb(base + DAC960_PD_ERRSTS_OFFSET);
3094 *param0 = readb(base + DAC960_PD_CMDOP_OFFSET);
3095 *param1 = readb(base + DAC960_PD_CMDID_OFFSET);
3096 writeb(0, base + DAC960_PD_ERRSTS_OFFSET);
3102 void __iomem *base = cb->io_base;
3105 while (DAC960_PD_hw_mbox_is_full(base))
3107 DAC960_PD_write_cmd_mbox(base, mbox);
3108 DAC960_PD_hw_mbox_new_cmd(base);
3112 struct myrb_hba *cb, void __iomem *base)
3122 DAC960_PD_disable_intr(base);
3123 DAC960_PD_ack_hw_mbox_status(base);
3125 while (DAC960_PD_init_in_progress(base) &&
3127 if (DAC960_PD_read_error_status(base, &error,
3142 DAC960_PD_reset_ctrl(base);
3145 DAC960_PD_enable_intr(base);
3156 void __iomem *base = cb->io_base;
3160 while (DAC960_PD_hw_mbox_status_available(base)) {
3161 unsigned char id = DAC960_PD_read_status_cmd_ident(base);
3175 cmd_blk->status = DAC960_PD_read_status(base);
3180 DAC960_PD_ack_intr(base);
3181 DAC960_PD_ack_hw_mbox_status(base);
3241 void __iomem *base = cb->io_base;
3270 while (DAC960_PD_hw_mbox_is_full(base))
3272 DAC960_PD_write_cmd_mbox(base, mbox);
3273 DAC960_PD_hw_mbox_new_cmd(base);
3278 struct myrb_hba *cb, void __iomem *base)
3288 DAC960_PD_disable_intr(base);
3289 DAC960_PD_ack_hw_mbox_status(base);
3291 while (DAC960_PD_init_in_progress(base) &&
3293 if (DAC960_PD_read_error_status(base, &error,
3308 DAC960_PD_reset_ctrl(base);
3311 DAC960_PD_enable_intr(base);
3322 void __iomem *base = cb->io_base;
3326 while (DAC960_PD_hw_mbox_status_available(base)) {
3327 unsigned char id = DAC960_PD_read_status_cmd_ident(base);
3344 cmd_blk->status = DAC960_PD_read_status(base);
3349 DAC960_PD_ack_intr(base);
3350 DAC960_PD_ack_hw_mbox_status(base);