Lines Matching refs:mw32
251 mw32(MVS_PCS, tmp);
324 mw32(MVS_HST_CHIP_CONFIG, tmp);
326 mw32(MVS_SGPIO_CTRL + MVS_SGPIO_HOST_OFFSET * mvi->id,
329 mw32(MVS_SGPIO_CFG1 + MVS_SGPIO_HOST_OFFSET * mvi->id,
338 mw32(MVS_SGPIO_CFG2 + MVS_SGPIO_HOST_OFFSET * mvi->id,
343 mw32(MVS_SGPIO_CFG0 + MVS_SGPIO_HOST_OFFSET * mvi->id,
351 mw32(MVS_SGPIO_DCTRL + MVS_SGPIO_HOST_OFFSET * mvi->id,
354 mw32(MVS_SGPIO_DSRC + MVS_SGPIO_HOST_OFFSET * mvi->id,
375 mw32(MVS_PHY_CTL, tmp);
392 mw32(MVS_PHY_CTL, tmp);
395 mw32(MVS_PHY_CTL, tmp);
400 mw32(MVS_PORTS_IMP, 0xFF);
403 mw32(MVS_PA_VSR_ADDR, CMD_CMWK_OOB_DET);
404 mw32(MVS_PA_VSR_PORT, 0x00018080);
406 mw32(MVS_PA_VSR_ADDR, VSR_PHY_MODE2);
409 mw32(MVS_PA_VSR_PORT, 0x0084d4fe);
412 mw32(MVS_PA_VSR_PORT, 0x0084fffe);
415 mw32(MVS_PA_VSR_ADDR, CMD_APP_MEM_CTL);
416 mw32(MVS_PA_VSR_PORT, 0x08001006);
417 mw32(MVS_PA_VSR_ADDR, CMD_HOST_RD_DATA);
418 mw32(MVS_PA_VSR_PORT, 0x0000705f);
422 mw32(MVS_PCS, 0); /* MVS_PCS */
423 mw32(MVS_STP_REG_SET_0, 0);
424 mw32(MVS_STP_REG_SET_1, 0);
440 mw32(MVS_PA_VSR_ADDR, VSR_PHY_ACT_LED);
444 mw32(MVS_PA_VSR_PORT, tmp);
446 mw32(MVS_CMD_LIST_LO, mvi->slot_dma);
447 mw32(MVS_CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);
449 mw32(MVS_RX_FIS_LO, mvi->rx_fis_dma);
450 mw32(MVS_RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);
452 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ);
453 mw32(MVS_TX_LO, mvi->tx_dma);
454 mw32(MVS_TX_HI, (mvi->tx_dma >> 16) >> 16);
456 mw32(MVS_RX_CFG, MVS_RX_RING_SZ);
457 mw32(MVS_RX_LO, mvi->rx_dma);
458 mw32(MVS_RX_HI, (mvi->rx_dma >> 16) >> 16);
512 mw32(MVS_PCS, tmp);
519 mw32(MVS_INT_COAL, 0x1ff | COAL_EN);
521 mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ | COAL_EN);
525 mw32(MVS_INT_COAL_TMOUT, tmp);
528 mw32(MVS_TX_CFG, 0);
529 mw32(MVS_TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN);
530 mw32(MVS_RX_CFG, MVS_RX_RING_SZ | RX_EN);
532 mw32(MVS_PCS, PCS_SATA_RETRY_2 | PCS_FIS_RX_EN |
539 mw32(MVS_INT_MASK, tmp);
563 mw32(MVS_INT_MASK_SRS_0, 0xFFFF);
599 mw32(MVS_GBL_INT_STAT, tmp);
604 mw32(MVS_GBL_CTL, tmp);
615 mw32(MVS_GBL_INT_STAT, tmp);
620 mw32(MVS_GBL_CTL, tmp);
676 mw32(MVS_INT_STAT_SRS_0, tmp);
681 mw32(MVS_INT_STAT_SRS_1, tmp);
692 mw32(MVS_INT_STAT_SRS_1, 1 << (reg_set % 32));
694 mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32));
707 mw32(MVS_INT_STAT, tmp | CINT_CI_STOP);
709 mw32(MVS_PCS, tmp);
737 mw32(MVS_NON_NCQ_ERR_0, err_0);
738 mw32(MVS_NON_NCQ_ERR_1, err_1);
916 mw32(MVS_STP_REG_SET_0, 0);
917 mw32(MVS_STP_REG_SET_0, tmp);
919 mw32(MVS_STP_REG_SET_1, 0);
920 mw32(MVS_STP_REG_SET_1, tmp);
934 mw32(SPI_RD_DATA_REG_94XX, data);
954 mw32(SPI_ADDR_REG_94XX, (addr & 0x0003FFFFL));
966 mw32(SPI_CTRL_REG_94XX, cmd | SPI_CTRL_SpiStart_94XX);
1027 mw32(MVS_INT_COAL, 0);
1028 mw32(MVS_INT_COAL_TMOUT, 0x10000);
1031 mw32(MVS_INT_COAL, 0x1ff|COAL_EN);
1033 mw32(MVS_INT_COAL, MVS_CHIP_SLOT_SZ|COAL_EN);
1036 mw32(MVS_INT_COAL_TMOUT, tmp);
1120 mw32(MVS_SGPIO_DCTRL + MVS_SGPIO_HOST_OFFSET * mvi->id,