Lines Matching defs:reply
504 #define MPT3_CMD_REPLY_VALID 0x0004 /* reply is valid */
512 * @reply: reply message pointer
520 void *reply;
934 * struct adapter_reply_queue - the reply queue struct
939 * @reply_post_free: reply post base virt address
945 * @is_iouring_poll_q: Tells whether reply queues is assigned
968 * @reply_q: reply queue mapped for io uring poll queue
999 * To get high iops reply queue's msix index when high iops mode is enabled
1000 * else get the msix index of general reply queues.
1194 * within high iops reply queues
1198 * @thresh_hold: Max number of reply descriptors processed
1201 * in reply queue list
1296 * @reply_depth: hba reply queue depth:
1297 * @reply_sz: per reply frame size:
1298 * @reply: pool of replys:
1301 * @reply_free_queue_depth: reply free depth
1302 * @reply_free: pool for reply free queue (32 bit addr)
1306 * @reply_post_queue_depth: reply post queue depth
1308 * @rdpq_array_capable: FW supports multiple reply queue addresses in ioc_init
1312 * @reply_queue_count: number of reply queue's
1313 * @reply_queue_list: link list contaning the reply queue info
1559 /* reply */
1561 u8 *reply;
1567 /* reply free queue */
1574 /* reply post queue */
1590 /* reply post register index */
1654 u32 reply);
1739 u32 reply);
1741 u8 msix_index, u32 reply);
1800 u32 reply);
1853 u32 reply);
1987 u32 reply);
1992 u8 msix_index, u32 reply);
2004 u32 reply);