Lines Matching refs:mr
305 volatile struct mesh_regs __iomem *mr = ms->mesh;
311 ms, mr, md);
314 (mr->count_hi << 8) + mr->count_lo, mr->sequence,
315 (mr->bus_status1 << 8) + mr->bus_status0, mr->fifo_count,
316 mr->exception, mr->error, mr->intr_mask, mr->interrupt,
317 mr->sync_params);
318 while(in_8(&mr->fifo_count))
319 printk(KERN_DEBUG " fifo data=%.2x\n",in_8(&mr->fifo));
339 static inline void mesh_flush_io(volatile struct mesh_regs __iomem *mr)
341 (void)in_8(&mr->mesh_id);
351 volatile struct mesh_regs __iomem *mr = ms->mesh;
354 mesh_flush_io(mr);
359 out_8(&mr->exception, 0xff); /* clear all exception bits */
360 out_8(&mr->error, 0xff); /* clear all error bits */
361 out_8(&mr->sequence, SEQ_RESETMESH);
362 mesh_flush_io(mr);
364 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
365 out_8(&mr->source_id, ms->host->this_id);
366 out_8(&mr->sel_timeout, 25); /* 250ms */
367 out_8(&mr->sync_params, ASYNC_PARAMS);
373 out_8(&mr->bus_status1, BS1_RST); /* assert RST */
374 mesh_flush_io(mr);
376 out_8(&mr->bus_status1, 0); /* negate RST */
377 mesh_flush_io(mr);
384 out_8(&mr->interrupt, 0xff); /* clear all interrupt bits */
385 out_8(&mr->sequence, SEQ_FLUSHFIFO);
386 mesh_flush_io(mr);
388 out_8(&mr->sync_params, ASYNC_PARAMS);
389 out_8(&mr->sequence, SEQ_ENBRESEL);
398 volatile struct mesh_regs __iomem *mr = ms->mesh;
437 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
438 out_8(&mr->interrupt, INT_CMDDONE);
439 out_8(&mr->sequence, SEQ_ENBRESEL);
440 mesh_flush_io(mr);
443 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) {
449 MKWORD(mr->interrupt, mr->exception,
450 mr->error, mr->fifo_count));
452 if ((in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) == 0)
454 if (in_8(&mr->interrupt) != 0) {
456 MKWORD(mr->interrupt, mr->exception,
457 mr->error, mr->fifo_count));
464 if (in_8(&mr->bus_status1) & (BS1_BSY | BS1_SEL)) {
477 out_8(&mr->dest_id, mr->source_id);
491 out_8(&mr->sequence, SEQ_DISRESEL);
492 if (in_8(&mr->interrupt) != 0) {
494 MKWORD(mr->interrupt, mr->exception,
495 mr->error, mr->fifo_count));
500 MKWORD(mr->interrupt, mr->exception,
501 mr->error, mr->fifo_count));
504 out_8(&mr->sequence, SEQ_ARBITRATE);
507 if (in_8(&mr->interrupt) != 0)
512 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
513 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL)
514 && (in_8(&mr->bus_status0) & BS0_IO)) {
517 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
518 out_8(&mr->sequence, SEQ_RESETMESH);
519 mesh_flush_io(mr);
521 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
522 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
523 out_8(&mr->sequence, SEQ_ENBRESEL);
524 mesh_flush_io(mr);
525 for (t = 10; t > 0 && in_8(&mr->interrupt) == 0; --t)
528 MKWORD(mr->interrupt, mr->exception, mr->error, mr->fifo_count));
530 if (in_8(&mr->interrupt) == 0 && (in_8(&mr->bus_status1) & BS1_SEL)
531 && (in_8(&mr->bus_status0) & BS0_IO)) {
635 volatile struct mesh_regs __iomem *mr = ms->mesh;
645 out_8(&mr->sync_params, ASYNC_PARAMS);
668 out_8(&mr->sync_params, tp->sync_params);
676 volatile struct mesh_regs __iomem *mr = ms->mesh;
682 MKWORD(ms->n_msgout, mr->exception, mr->fifo_count, mr->sequence));
683 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
690 out_8(&mr->count_hi, 0);
691 out_8(&mr->count_lo, 1);
692 out_8(&mr->sequence, SEQ_MSGIN + seq);
718 out_8(&mr->count_hi, 0);
719 out_8(&mr->sequence, SEQ_FLUSHFIFO);
720 mesh_flush_io(mr);
726 if ((in_8(&mr->bus_status0) & BS0_ATN) == 0) {
727 dlog(ms, "bus0 was %.2x explicitly asserting ATN", mr->bus_status0);
728 out_8(&mr->bus_status0, BS0_ATN); /* explicit ATN */
729 mesh_flush_io(mr);
731 out_8(&mr->count_lo, 1);
732 out_8(&mr->sequence, SEQ_MSGOUT + seq);
733 out_8(&mr->bus_status0, 0); /* release explicit ATN */
734 dlog(ms,"hace: after explicit ATN bus0=%.2x",mr->bus_status0);
745 out_8(&mr->count_lo, ms->n_msgout - 1);
746 out_8(&mr->sequence, SEQ_MSGOUT + seq);
748 out_8(&mr->fifo, ms->msgout[i]);
759 out_8(&mr->dest_id, ms->conn_tgt);
760 out_8(&mr->sequence, SEQ_SELECT + SEQ_ATN);
763 out_8(&mr->sync_params, tp->sync_params);
764 out_8(&mr->count_hi, 0);
766 out_8(&mr->count_lo, cmd->cmd_len);
767 out_8(&mr->sequence, SEQ_COMMAND + seq);
769 out_8(&mr->fifo, cmd->cmnd[i]);
771 out_8(&mr->count_lo, 6);
772 out_8(&mr->sequence, SEQ_COMMAND + seq);
774 out_8(&mr->fifo, 0);
790 out_8(&mr->count_lo, nb);
791 out_8(&mr->count_hi, nb >> 8);
792 out_8(&mr->sequence, (tp->data_goes_out?
796 out_8(&mr->count_hi, 0);
797 out_8(&mr->count_lo, 1);
798 out_8(&mr->sequence, SEQ_STATUS + seq);
802 out_8(&mr->sequence, SEQ_ENBRESEL);
803 mesh_flush_io(mr);
806 MKWORD(mr->interrupt, mr->exception, mr->error,
807 mr->fifo_count));
808 out_8(&mr->sequence, SEQ_BUSFREE);
820 volatile struct mesh_regs __iomem *mr = ms->mesh;
823 n = mr->fifo_count;
828 ms->msgin[i++] = in_8(&mr->fifo);
852 volatile struct mesh_regs __iomem *mr = ms->mesh;
898 while ((in_8(&mr->bus_status1) & BS1_BSY) == 0) {
901 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
902 mesh_flush_io(mr);
904 out_8(&mr->sequence, SEQ_ENBRESEL);
905 mesh_flush_io(mr);
908 MKWORD(0, mr->error, mr->exception, mr->fifo_count));
910 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
911 mesh_flush_io(mr);
913 out_8(&mr->sequence, SEQ_ENBRESEL);
914 mesh_flush_io(mr);
916 out_8(&mr->sync_params, ASYNC_PARAMS);
921 if (in_8(&mr->fifo_count) == 0) {
928 b = in_8(&mr->fifo);
930 } while (in_8(&mr->fifo_count));
946 out_8(&mr->sync_params, tp->sync_params);
959 dlog(ms, "resel err/exc=%.4x", MKWORD(0, 0, mr->error, mr->exception));
985 volatile struct mesh_regs __iomem *mr = ms->mesh;
1005 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1006 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1007 mesh_flush_io(mr);
1009 out_8(&mr->sync_params, ASYNC_PARAMS);
1010 out_8(&mr->sequence, SEQ_ENBRESEL);
1028 volatile struct mesh_regs __iomem *mr = ms->mesh;
1030 err = in_8(&mr->error);
1031 exc = in_8(&mr->exception);
1032 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1034 MKWORD(err, exc, mr->fifo_count, mr->count_lo));
1039 while ((in_8(&mr->bus_status1) & BS1_RST) != 0)
1060 out_8(&mr->interrupt, INT_CMDDONE);
1080 count = (mr->count_hi << 8) + mr->count_lo;
1085 out_8(&mr->sequence, mr->sequence);
1111 if (ms->phase > selecting && (in_8(&mr->bus_status1) & BS1_BSY)) {
1124 volatile struct mesh_regs __iomem *mr = ms->mesh;
1126 exc = in_8(&mr->exception);
1127 out_8(&mr->interrupt, INT_EXCEPTION | INT_CMDDONE);
1318 volatile struct mesh_regs __iomem *mr = ms->mesh;
1325 while (t > 0 && in_8(&mr->fifo_count) != 0
1332 nb = (mr->count_hi << 8) + mr->count_lo;
1334 MKWORD(0, mr->fifo_count, 0, nb));
1336 nb += mr->fifo_count;
1363 volatile struct mesh_regs __iomem *mr = ms->mesh;
1367 MKWORD(mr->count_hi, mr->count_lo, mr->sequence, mr->fifo_count));
1368 phase = in_8(&mr->bus_status0) & BS0_PHASE;
1371 out_8(&mr->count_lo, 1);
1372 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1373 mesh_flush_io(mr);
1375 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1388 if (mr->fifo_count) {
1389 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1390 mesh_flush_io(mr);
1442 volatile struct mesh_regs __iomem *mr = ms->mesh;
1447 dlog(ms, "cmd_complete fc=%x", mr->fifo_count);
1461 out_8(&mr->count_lo, n - ms->n_msgin);
1462 out_8(&mr->sequence, SEQ_MSGIN + seq);
1471 out_8(&mr->sequence, SEQ_FLUSHFIFO);
1472 mesh_flush_io(mr);
1474 out_8(&mr->count_lo, 1);
1475 out_8(&mr->sequence, SEQ_MSGIN + SEQ_ATN + use_active_neg);
1490 out_8(&mr->count_lo, 1);
1491 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg + SEQ_ATN);
1493 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0 && --t >= 0)
1496 MKWORD(mr->error, mr->exception,
1497 mr->fifo_count, mr->count_lo));
1498 if (in_8(&mr->interrupt) & (INT_ERROR | INT_EXCEPTION)) {
1502 if (in_8(&mr->interrupt) & INT_ERROR) {
1504 in_8(&mr->error));
1508 if (in_8(&mr->exception) != EXC_PHASEMM)
1510 in_8(&mr->exception));
1513 in_8(&mr->bus_status0));
1517 if (in_8(&mr->bus_status0) & BS0_REQ) {
1518 out_8(&mr->sequence, SEQ_MSGOUT + use_active_neg);
1519 mesh_flush_io(mr);
1521 out_8(&mr->fifo, ms->msgout[ms->n_msgout-1]);
1524 out_8(&mr->sequence, SEQ_MSGIN + use_active_neg + SEQ_ATN);
1566 while ((in_8(&mr->bus_status0) & BS0_REQ) == 0) {
1590 out_8(&mr->sequence, 0);
1591 out_8(&mr->interrupt,
1599 mcmd->status = mr->fifo;
1657 volatile struct mesh_regs __iomem *mr = ms->mesh;
1663 "phase=%d msgphase=%d\n", mr->bus_status0,
1664 mr->interrupt, mr->exception, mr->error,
1667 while ((intr = in_8(&mr->interrupt)) != 0) {
1669 MKWORD(intr, mr->error, mr->exception, mr->sequence));
1675 out_8(&mr->interrupt, INT_CMDDONE);
1705 volatile struct mesh_regs __iomem *mr = ms->mesh;
1718 out_8(&mr->exception, 0xff); /* clear all exception bits */
1719 out_8(&mr->error, 0xff); /* clear all error bits */
1720 out_8(&mr->sequence, SEQ_RESETMESH);
1721 mesh_flush_io(mr);
1723 out_8(&mr->intr_mask, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1724 out_8(&mr->source_id, ms->host->this_id);
1725 out_8(&mr->sel_timeout, 25); /* 250ms */
1726 out_8(&mr->sync_params, ASYNC_PARAMS);
1729 out_8(&mr->bus_status1, BS1_RST); /* assert RST */
1730 mesh_flush_io(mr);
1732 out_8(&mr->bus_status1, 0); /* negate RST */
1816 volatile struct mesh_regs __iomem *mr;
1821 mr = ms->mesh;
1822 out_8(&mr->intr_mask, 0);
1823 out_8(&mr->interrupt, INT_ERROR | INT_EXCEPTION | INT_CMDDONE);
1824 out_8(&mr->bus_status1, BS1_RST);
1825 mesh_flush_io(mr);
1827 out_8(&mr->bus_status1, 0);