Lines Matching refs:mem_ptr
2052 (unsigned long)ha->mem_ptr);
2252 writel(0, ha->mem_ptr + IPS_REG_FLAP);
2256 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
2259 writel(1, ha->mem_ptr + IPS_REG_FLAP);
2263 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
2267 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
2271 major = readb(ha->mem_ptr + IPS_REG_FLDP);
2274 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
2277 minor = readb(ha->mem_ptr + IPS_REG_FLDP);
2280 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
2283 subminor = readb(ha->mem_ptr + IPS_REG_FLDP);
4258 if (ha->mem_ptr) {
4261 ha->mem_ptr = NULL;
4504 isr = readb(ha->mem_ptr + IPS_REG_HISR);
4505 scpr = readb(ha->mem_ptr + IPS_REG_SCPR);
4533 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4534 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4663 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4664 readb(ha->mem_ptr + IPS_REG_HISR); /*Ensure PCI Posting Completes*/
4682 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4684 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4685 readl(ha->mem_ptr + IPS_REG_I960_OIMR); /*Ensure PCI Posting Completes*/
4802 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4814 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4815 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4828 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4840 readb(ha->mem_ptr + IPS_REG_ISPR);
4841 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4845 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);
4859 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);
4862 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);
4866 writel(0, ha->mem_ptr + IPS_REG_NDAE);
4869 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4897 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4914 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4922 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4925 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4942 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4953 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4970 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
4974 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4977 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4979 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
5061 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);
5066 writeb(0, ha->mem_ptr + IPS_REG_SCPR);
5107 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);
5178 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);
5180 ha->mem_ptr + IPS_REG_SQER);
5181 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);
5182 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);
5237 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);
5258 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);
5348 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {
5364 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);
5365 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);
5429 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);
5483 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5494 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5516 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
6136 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6140 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6145 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);
6150 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);
6155 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);
6163 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6167 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6181 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);
6189 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6193 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6217 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6222 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6342 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6346 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);
6350 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);
6358 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6362 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6373 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6377 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6387 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6391 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6400 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6404 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6478 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6482 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
6485 writel(1, ha->mem_ptr + IPS_REG_FLAP);
6488 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
6494 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6499 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);
6843 char __iomem *mem_ptr;
6887 mem_ptr = ioremap_ptr + offs;
6890 mem_ptr = NULL;
6910 ha->mem_ptr = mem_ptr;
7012 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);