Lines Matching refs:mu
142 static u64 mv_outbound_read(struct hpt_iopmu_mv __iomem *mu)
144 u32 outbound_tail = readl(&mu->outbound_tail);
145 u32 outbound_head = readl(&mu->outbound_head);
150 memcpy_fromio(&p, &mu->outbound_q[mu->outbound_tail], 8);
155 writel(outbound_tail, &mu->outbound_tail);
163 u32 inbound_head = readl(&hba->u.mv.mu->inbound_head);
169 memcpy_toio(&hba->u.mv.mu->inbound_q[inbound_head], &p, 8);
170 writel(head, &hba->u.mv.mu->inbound_head);
213 msg = readl(&hba->u.mv.mu->outbound_msg);
222 while ((tag = mv_outbound_read(hba->u.mv.mu)))
259 writel(0, &(hba->u.mvfrey.mu->pcie_f0_int_enable));
261 status = readl(&(hba->u.mvfrey.mu->f0_doorbell));
263 writel(status, &(hba->u.mvfrey.mu->f0_doorbell));
265 u32 msg = readl(&(hba->u.mvfrey.mu->cpu_to_f0_msg_a));
272 status = readl(&(hba->u.mvfrey.mu->isr_cause));
274 writel(status, &(hba->u.mvfrey.mu->isr_cause));
293 writel(0x1010, &(hba->u.mvfrey.mu->pcie_f0_int_enable));
368 writel(msg, &hba->u.mv.mu->inbound_msg);
375 writel(msg, &(hba->u.mvfrey.mu->f0_to_cpu_msg_a));
376 readl(&(hba->u.mvfrey.mu->f0_to_cpu_msg_a));
563 writel(CPU_TO_F0_DRBL_MSG_BIT, &(hba->u.mvfrey.mu->f0_doorbell_enable));
564 writel(0x1, &(hba->u.mvfrey.mu->isr_enable));
565 writel(0x1010, &(hba->u.mvfrey.mu->pcie_f0_int_enable));
641 hba->u.mv.mu = hptiop_map_pci_bar(hba, 2);
642 if (hba->u.mv.mu == NULL) {
656 hba->u.mvfrey.mu = hptiop_map_pci_bar(hba, 2);
657 if (hba->u.mvfrey.mu == NULL) {
668 iounmap(hba->u.mv.mu);
674 iounmap(hba->u.mvfrey.mu);
951 &(hba->u.mvfrey.mu->inbound_write_ptr));
952 readl(&(hba->u.mvfrey.mu->inbound_write_ptr));
976 &(hba->u.mvfrey.mu->inbound_base));
978 &(hba->u.mvfrey.mu->inbound_base_high));
981 &(hba->u.mvfrey.mu->outbound_base));
983 &(hba->u.mvfrey.mu->outbound_base_high));
986 &(hba->u.mvfrey.mu->outbound_shadow_base));
988 &(hba->u.mvfrey.mu->outbound_shadow_base_high));
1194 u32 list_count = readl(&hba->u.mvfrey.mu->inbound_conf_ctl);
1537 writel(0, &(hba->u.mvfrey.mu->f0_doorbell_enable));
1538 readl(&(hba->u.mvfrey.mu->f0_doorbell_enable));
1539 writel(0, &(hba->u.mvfrey.mu->isr_enable));
1540 readl(&(hba->u.mvfrey.mu->isr_enable));
1541 writel(0, &(hba->u.mvfrey.mu->pcie_f0_int_enable));
1542 readl(&(hba->u.mvfrey.mu->pcie_f0_int_enable));