Lines Matching defs:reg
146 u32 reg;
148 reg = (id & SLI4_EQ_ID_LO_MASK) | SLI4_EQCQ_QT_EQ;
149 reg |= (((id) >> 9) << SLI4_EQCQ_ID_HI_SHIFT) & SLI4_EQCQ_ID_HI_MASK;
150 reg |= ((num_popped) << SLI4_EQCQ_NUM_SHIFT) & SLI4_EQCQ_NUM_MASK;
151 reg |= arm | SLI4_EQCQ_CI_EQ;
153 return reg;
158 u32 reg;
160 reg = ((id) & SLI4_CQ_ID_LO_MASK) | SLI4_EQCQ_QT_CQ;
161 reg |= (((id) >> 10) << SLI4_EQCQ_ID_HI_SHIFT) & SLI4_EQCQ_ID_HI_MASK;
162 reg |= ((num_popped) << SLI4_EQCQ_NUM_SHIFT) & SLI4_EQCQ_NUM_MASK;
163 reg |= arm;
165 return reg;
179 u32 reg;
181 reg = id & SLI4_IF6_EQ_ID_MASK;
182 reg |= (num_popped << SLI4_IF6_EQ_NUM_SHIFT) & SLI4_IF6_EQ_NUM_MASK;
183 reg |= arm;
185 return reg;
199 u32 reg;
201 reg = id & SLI4_IF6_CQ_ID_MASK;
202 reg |= ((num_popped) << SLI4_IF6_CQ_NUM_SHIFT) & SLI4_IF6_CQ_NUM_MASK;
203 reg |= arm;
205 return reg;
220 u32 reg;
222 reg = id & SLI4_MQ_ID_MASK;
223 reg |= (1 << SLI4_MQ_NUM_SHIFT) & SLI4_MQ_NUM_MASK;
225 return reg;
240 u32 reg;
242 reg = id & SLI4_RQ_DB_ID_MASK;
243 reg |= (1 << SLI4_RQ_DB_NUM_SHIFT) & SLI4_RQ_DB_NUM_MASK;
245 return reg;
263 u32 reg;
265 reg = id & SLI4_WQ_ID_MASK;
266 reg |= (1 << SLI4_WQ_NUM_SHIFT) & SLI4_WQ_NUM_MASK;
268 return reg;
3663 void __iomem *reg[PCI_STD_NUM_BARS];
3808 return readl(sli->reg[0] + SLI4_PORT_STATUS_REGOFF);
3820 return readl(sli->reg[0] + SLI4_PORT_ERROR1);
3826 return readl(sli->reg[0] + SLI4_PORT_ERROR2);