Lines Matching defs:sli4
11 #include "sli4.h"
37 * @sli4: SLI context pointer.
44 sli_config_cmd_init(struct sli4 *sli4, void *buf, u32 length,
51 efc_log_err(sli4, "Too big for an embedded cmd with len(%d)\n",
78 sli4->bmbx_non_emb_pmd = dma;
85 * @sli4: SLI context pointer.
92 sli_cmd_common_create_cq(struct sli4 *sli4, void *buf, struct efc_dma *qmem,
126 cqv2 = sli_config_cmd_init(sli4, buf, cmd_size, NULL);
155 efc_log_err(sli4, "num_pages %d not valid\n", num_pages);
159 if (sli4->if_type == SLI4_INTF_IF_TYPE_6)
178 sli_cmd_common_create_eq(struct sli4 *sli4, void *buf, struct efc_dma *qmem)
187 eq = sli_config_cmd_init(sli4, buf, SLI4_CFG_PYLD_LENGTH(cmn_create_eq),
192 if (sli4->if_type == SLI4_INTF_IF_TYPE_6)
218 efc_log_err(sli4, "num_pages %d not valid\n", num_pages);
222 if (sli4->if_type == SLI4_INTF_IF_TYPE_6)
241 sli_cmd_common_create_mq_ext(struct sli4 *sli4, void *buf, struct efc_dma *qmem,
250 mq = sli_config_cmd_init(sli4, buf,
276 efc_log_info(sli4, "num_pages %d not valid\n", num_pages);
282 if (sli4->params.mq_create_version) {
301 sli_cmd_wq_create(struct sli4 *sli4, void *buf, struct efc_dma *qmem, u16 cq_id)
310 wq = sli_config_cmd_init(sli4, buf, SLI4_CFG_PYLD_LENGTH(wq_create),
317 n_wqe = qmem->size / sli4->wqe_size;
352 if (sli4->wqe_size == SLI4_WQE_EXT_BYTES)
368 sli_cmd_rq_create_v1(struct sli4 *sli4, void *buf, struct efc_dma *qmem,
376 rq = sli_config_cmd_init(sli4, buf, SLI4_CFG_PYLD_LENGTH(rq_create_v1),
391 efc_log_info(sli4, "num_pages %d not valid, max %d\n",
405 if (buffer_size < sli4->rq_min_buf_size ||
406 buffer_size > sli4->rq_max_buf_size) {
407 efc_log_err(sli4, "buffer_size %d out of range (%d-%d)\n",
408 buffer_size, sli4->rq_min_buf_size,
409 sli4->rq_max_buf_size);
427 sli_cmd_rq_create_v2(struct sli4 *sli4, u32 num_rqs,
447 dma->virt = dma_alloc_coherent(&sli4->pci->dev, dma->size,
454 req = sli_config_cmd_init(sli4, sli4->bmbx.virt, payload_size, dma);
488 __sli_queue_destroy(struct sli4 *sli4, struct sli4_queue *q)
493 dma_free_coherent(&sli4->pci->dev, q->dma.size,
499 __sli_queue_init(struct sli4 *sli4, struct sli4_queue *q, u32 qtype,
503 efc_log_err(sli4, "%s failed\n", __func__);
510 q->dma.virt = dma_alloc_coherent(&sli4->pci->dev, q->dma.size,
514 efc_log_err(sli4, "%s allocation failed\n", SLI4_QNAME[qtype]);
545 sli_fc_rq_alloc(struct sli4 *sli4, struct sli4_queue *q,
549 if (__sli_queue_init(sli4, q, SLI4_QTYPE_RQ, SLI4_RQE_SIZE,
553 if (sli_cmd_rq_create_v1(sli4, sli4->bmbx.virt, &q->dma, cq->id,
557 if (__sli_create_queue(sli4, q))
561 efc_log_info(sli4, "bad header RQ_ID %d\n", q->id);
564 efc_log_info(sli4, "bad data RQ_ID %d\n", q->id);
576 __sli_queue_destroy(sli4, q);
581 sli_fc_rq_set_alloc(struct sli4 *sli4, u32 num_rq_pairs,
593 if (__sli_queue_init(sli4, qs[i], SLI4_QTYPE_RQ,
600 if (sli_cmd_rq_create_v2(sli4, num_rqs, qs, base_cq_id,
606 if (sli_bmbx_command(sli4)) {
607 efc_log_err(sli4, "bootstrap mailbox write failed RQSet\n");
611 if (sli4->if_type == SLI4_INTF_IF_TYPE_6)
612 db_regaddr = sli4->reg[1] + SLI4_IF6_RQ_DB_REG;
614 db_regaddr = sli4->reg[0] + SLI4_RQ_DB_REG;
618 efc_log_err(sli4, "bad create RQSet status=%#x addl=%#x\n",
633 dma_free_coherent(&sli4->pci->dev, dma.size, dma.virt, dma.phys);
639 __sli_queue_destroy(sli4, qs[i]);
642 dma_free_coherent(&sli4->pci->dev, dma.size, dma.virt,
649 sli_res_sli_config(struct sli4 *sli4, void *buf)
656 efc_log_err(sli4, "bad parameter buf=%p cmd=%#x\n", buf,
667 efc_log_info(sli4, "external buffers not supported\n");
672 __sli_create_queue(struct sli4 *sli4, struct sli4_queue *q)
676 if (sli_bmbx_command(sli4)) {
677 efc_log_crit(sli4, "bootstrap mailbox write fail %s\n",
681 if (sli_res_sli_config(sli4, sli4->bmbx.virt)) {
682 efc_log_err(sli4, "bad status create %s\n",
686 res_q = (void *)((u8 *)sli4->bmbx.virt +
690 efc_log_err(sli4, "bad create %s status=%#x addl=%#x\n",
698 if (sli4->if_type == SLI4_INTF_IF_TYPE_6)
699 q->db_regaddr = sli4->reg[1] + SLI4_IF6_EQ_DB_REG;
701 q->db_regaddr = sli4->reg[0] + SLI4_EQCQ_DB_REG;
704 if (sli4->if_type == SLI4_INTF_IF_TYPE_6)
705 q->db_regaddr = sli4->reg[1] + SLI4_IF6_CQ_DB_REG;
707 q->db_regaddr = sli4->reg[0] + SLI4_EQCQ_DB_REG;
710 if (sli4->if_type == SLI4_INTF_IF_TYPE_6)
711 q->db_regaddr = sli4->reg[1] + SLI4_IF6_MQ_DB_REG;
713 q->db_regaddr = sli4->reg[0] + SLI4_MQ_DB_REG;
716 if (sli4->if_type == SLI4_INTF_IF_TYPE_6)
717 q->db_regaddr = sli4->reg[1] + SLI4_IF6_RQ_DB_REG;
719 q->db_regaddr = sli4->reg[0] + SLI4_RQ_DB_REG;
722 if (sli4->if_type == SLI4_INTF_IF_TYPE_6)
723 q->db_regaddr = sli4->reg[1] + SLI4_IF6_WQ_DB_REG;
725 q->db_regaddr = sli4->reg[0] + SLI4_IO_WQ_DB_REG;
735 sli_get_queue_entry_size(struct sli4 *sli4, u32 qtype)
750 size = sli4->wqe_size;
756 efc_log_info(sli4, "unknown queue type %d\n", qtype);
763 sli_queue_alloc(struct sli4 *sli4, u32 qtype,
771 size = sli_get_queue_entry_size(sli4, qtype);
776 if (__sli_queue_init(sli4, q, qtype, size, n_entries, align))
781 if (!sli_cmd_common_create_eq(sli4, sli4->bmbx.virt, &q->dma) &&
782 !__sli_create_queue(sli4, q))
787 if (!sli_cmd_common_create_cq(sli4, sli4->bmbx.virt, &q->dma,
789 !__sli_create_queue(sli4, q))
795 if (!sli_cmd_common_create_mq_ext(sli4, sli4->bmbx.virt,
797 !__sli_create_queue(sli4, q))
802 if (!sli_cmd_wq_create(sli4, sli4->bmbx.virt, &q->dma,
804 !__sli_create_queue(sli4, q))
809 efc_log_info(sli4, "unknown queue type %d\n", qtype);
812 __sli_queue_destroy(sli4, q);
816 static int sli_cmd_cq_set_create(struct sli4 *sli4,
851 dma->virt = dma_alloc_coherent(&sli4->pci->dev, dma->size,
858 req = sli_config_cmd_init(sli4, sli4->bmbx.virt, payload_size, dma);
884 efc_log_info(sli4, "num_pages %d not valid\n", num_pages_cq);
890 if (sli4->if_type == SLI4_INTF_IF_TYPE_6)
917 sli_cq_alloc_set(struct sli4 *sli4, struct sli4_queue *qs[],
927 if (__sli_queue_init(sli4, qs[i], SLI4_QTYPE_CQ, SLI4_CQE_BYTES,
932 if (sli_cmd_cq_set_create(sli4, qs, num_cqs, eqs, &dma))
935 if (sli_bmbx_command(sli4))
938 if (sli4->if_type == SLI4_INTF_IF_TYPE_6)
939 db_regaddr = sli4->reg[1] + SLI4_IF6_CQ_DB_REG;
941 db_regaddr = sli4->reg[0] + SLI4_EQCQ_DB_REG;
945 efc_log_err(sli4, "bad create CQSet status=%#x addl=%#x\n",
952 efc_log_crit(sli4, "Requested count CQs doesn't match.\n");
961 dma_free_coherent(&sli4->pci->dev, dma.size, dma.virt, dma.phys);
967 __sli_queue_destroy(sli4, qs[i]);
970 dma_free_coherent(&sli4->pci->dev, dma.size, dma.virt,
977 sli_cmd_common_destroy_q(struct sli4 *sli4, u8 opc, u8 subsystem, u16 q_id)
982 req = sli_config_cmd_init(sli4, sli4->bmbx.virt,
995 sli_queue_free(struct sli4 *sli4, struct sli4_queue *q,
1003 efc_log_err(sli4, "bad parameter sli4=%p q=%p\n", sli4, q);
1032 efc_log_info(sli4, "bad queue type %d\n", q->type);
1037 rc = sli_cmd_common_destroy_q(sli4, opcode, subsystem, q->id);
1041 rc = sli_bmbx_command(sli4);
1045 rc = sli_res_sli_config(sli4, sli4->bmbx.virt);
1049 res = (void *)((u8 *)sli4->bmbx.virt +
1052 efc_log_err(sli4, "destroy %s st=%#x addl=%#x\n",
1061 __sli_queue_destroy(sli4, q);
1067 sli_queue_eq_arm(struct sli4 *sli4, struct sli4_queue *q, bool arm)
1074 if (sli4->if_type == SLI4_INTF_IF_TYPE_6)
1087 sli_queue_arm(struct sli4 *sli4, struct sli4_queue *q, bool arm)
1097 if (sli4->if_type == SLI4_INTF_IF_TYPE_6)
1106 if (sli4->if_type == SLI4_INTF_IF_TYPE_6)
1115 efc_log_info(sli4, "should only be used for EQ/CQ, not %s\n",
1125 sli_wq_write(struct sli4 *sli4, struct sli4_queue *q, u8 *entry)
1134 if (sli4->params.perf_wq_id_association)
1147 sli_mq_write(struct sli4 *sli4, struct sli4_queue *q, u8 *entry)
1168 sli_rq_write(struct sli4 *sli4, struct sli4_queue *q, u8 *entry)
1197 sli_eq_read(struct sli4 *sli4, struct sli4_queue *q, u8 *entry)
1215 if (sli4->if_type != SLI4_INTF_IF_TYPE_6) {
1230 if (sli4->if_type == SLI4_INTF_IF_TYPE_6 && q->index == 0)
1239 sli_cq_read(struct sli4 *sli4, struct sli4_queue *q, u8 *entry)
1259 if (sli4->if_type != SLI4_INTF_IF_TYPE_6) {
1274 if (sli4->if_type == SLI4_INTF_IF_TYPE_6 && q->index == 0)
1283 sli_mq_read(struct sli4 *sli4, struct sli4_queue *q, u8 *entry)
1307 sli_eq_parse(struct sli4 *sli4, u8 *buf, u16 *cq_id)
1316 efc_log_err(sli4, "bad parameters sli4=%p buf=%p cq_id=%p\n",
1317 sli4, buf, cq_id);
1329 efc_log_info(sli4, "sentinel EQE\n");
1333 efc_log_info(sli4, "Unsupported EQE: major %x minor %x\n",
1342 sli_cq_parse(struct sli4 *sli4, struct sli4_queue *cq, u8 *cqe,
1348 efc_log_err(sli4, "bad params sli4=%p cq=%p cqe=%p etype=%p q_id=%p\n",
1349 sli4, cq, cqe, etype, q_id);
1361 rc = sli_cqe_mq(sli4, mcqe);
1365 rc = sli_fc_cqe_parse(sli4, cq, cqe, etype, q_id);
1372 sli_abort_wqe(struct sli4 *sli, void *buf, enum sli4_abort_type type,
1418 sli_els_request64_wqe(struct sli4 *sli, void *buf, struct efc_dma *sgl,
1563 sli_fcp_icmnd64_wqe(struct sli4 *sli, void *buf, struct efc_dma *sgl, u16 xri,
1628 sli_fcp_iread64_wqe(struct sli4 *sli, void *buf, struct efc_dma *sgl,
1729 sli_fcp_iwrite64_wqe(struct sli4 *sli, void *buf, struct efc_dma *sgl,
1823 sli_fcp_treceive64_wqe(struct sli4 *sli, void *buf, struct efc_dma *sgl,
1941 sli_fcp_cont_treceive64_wqe(struct sli4 *sli, void *buf,
1960 sli_fcp_trsp64_wqe(struct sli4 *sli4, void *buf, struct efc_dma *sgl,
1966 memset(buf, 0, sli4->wqe_size);
1974 if (sli4->params.sgl_pre_registered || port_owned)
2016 if (params->app_id && sli4->wqe_size == SLI4_WQE_EXT_BYTES &&
2026 sli_fcp_tsend64_wqe(struct sli4 *sli4, void *buf, struct efc_dma *sgl,
2035 memset(buf, 0, sli4->wqe_size);
2038 efc_log_err(sli4, "bad parameter sgl=%p virt=%p\n",
2045 if (sli4->params.sgl_pre_registered) {
2124 if (sli4->params.perf_hint) {
2142 if (params->app_id && sli4->wqe_size == SLI4_WQE_EXT_BYTES &&
2152 sli_gen_request64_wqe(struct sli4 *sli4, void *buf, struct efc_dma *sgl,
2159 memset(buf, 0, sli4->wqe_size);
2162 efc_log_err(sli4, "bad parameter sgl=%p virt=%p\n",
2169 if (sli4->params.sgl_pre_registered) {
2225 sli_send_frame_wqe(struct sli4 *sli, void *buf, u8 sof, u8 eof, u32 *hdr,
2275 sli_xmit_bls_rsp64_wqe(struct sli4 *sli, void *buf,
2348 sli_xmit_els_rsp64_wqe(struct sli4 *sli, void *buf, struct efc_dma *rsp,
2406 sli_xmit_sequence64_wqe(struct sli4 *sli4, void *buf, struct efc_dma *payload,
2411 memset(buf, 0, sli4->wqe_size);
2414 efc_log_err(sli4, "bad parameter sgl=%p virt=%p\n",
2419 if (sli4->params.sgl_pre_registered)
2478 sli_requeue_xri_wqe(struct sli4 *sli4, void *buf, u16 xri, u16 tag, u16 cq_id)
2482 memset(buf, 0, sli4->wqe_size);
2495 sli_fc_process_link_attention(struct sli4 *sli4, void *acqe)
2500 efc_log_info(sli4, "link=%d attn_type=%#x top=%#x speed=%#x pfault=%#x\n",
2504 efc_log_info(sli4, "shared_lnk_status=%#x logl_lnk_speed=%#x evttag=%#x\n",
2509 if (!sli4->link)
2522 efc_log_info(sli4, "attn_type: no hard alpa\n");
2526 efc_log_info(sli4, "attn_type: unknown\n");
2534 efc_log_info(sli4, "event_type: FC shared link event\n");
2537 efc_log_info(sli4, "event_type: unknown\n");
2549 efc_log_info(sli4, "topology Internal loopback\n");
2553 efc_log_info(sli4, "topology serdes loopback\n");
2557 efc_log_info(sli4, "topology: unknown\n");
2563 sli4->link(sli4->link_arg, (void *)&event);
2569 sli_fc_cqe_parse(struct sli4 *sli4, struct sli4_queue *cq,
2586 efc_log_info(sli4, "WCQE: status=%#x hw_status=%#x tag=%#x\n",
2589 efc_log_info(sli4, "w1=%#x w2=%#x xb=%d\n",
2593 efc_log_info(sli4, " %08X %08X %08X %08X\n",
2637 efc_log_info(sli4, "Optimized DATA CQE: status=%#x\n",
2639 efc_log_info(sli4, "hstat=%#x xri=%#x dpl=%#x w3=%#x xb=%d\n",
2675 efc_log_info(sli4, "CQE completion code %d not handled\n",
2686 sli_fc_response_length(struct sli4 *sli4, u8 *cqe)
2694 sli_fc_io_length(struct sli4 *sli4, u8 *cqe)
2702 sli_fc_els_did(struct sli4 *sli4, u8 *cqe, u32 *d_id)
2715 sli_fc_ext_status(struct sli4 *sli4, u8 *cqe)
2746 sli_fc_rqe_rqid_and_index(struct sli4 *sli4, u8 *cqe, u16 *rq_id, u32 *index)
2769 efc_log_info(sli4, "status=%02x (%s) rq_id=%d\n",
2775 efc_log_info(sli4, "pdpl=%x sof=%02x eof=%02x hdpl=%x\n",
2792 efc_log_info(sli4, "status=%02x (%s) rq_id=%d, index=%x\n",
2797 efc_log_info(sli4, "pdpl=%x sof=%02x eof=%02x hdpl=%x\n",
2811 efc_log_info(sli4, "stat=%02x (%s) rqid=%d, idx=%x pdpl=%x\n",
2817 efc_log_info(sli4, "hdpl=%x oox=%d agxr=%d xri=0x%x rpi=%x\n",
2837 efc_log_info(sli4, "stat=%02x (%s) rq_id=%d, idx=%x\n",
2841 efc_log_info(sli4, "rq_id=%#x sdpl=%x\n",
2851 efc_log_info(sli4, "status=%02x rq_id=%d, index=%x pdpl=%x\n",
2856 efc_log_info(sli4, "sof=%02x eof=%02x hdpl=%x\n",
2865 sli_bmbx_wait(struct sli4 *sli4, u32 msec)
2873 val = readl(sli4->reg[0] + SLI4_BMBX_REG);
2884 sli_bmbx_write(struct sli4 *sli4)
2889 val = sli_bmbx_write_hi(sli4->bmbx.phys);
2890 writel(val, (sli4->reg[0] + SLI4_BMBX_REG));
2892 if (sli_bmbx_wait(sli4, SLI4_BMBX_DELAY_US)) {
2893 efc_log_crit(sli4, "BMBX WRITE_HI failed\n");
2896 val = sli_bmbx_write_lo(sli4->bmbx.phys);
2897 writel(val, (sli4->reg[0] + SLI4_BMBX_REG));
2900 return sli_bmbx_wait(sli4, SLI4_BMBX_TIMEOUT_MSEC);
2904 sli_bmbx_command(struct sli4 *sli4)
2906 void *cqe = (u8 *)sli4->bmbx.virt + SLI4_BMBX_SIZE;
2908 if (sli_fw_error_status(sli4) > 0) {
2909 efc_log_crit(sli4, "Chip is in an error state -Mailbox command rejected");
2910 efc_log_crit(sli4, " status=%#x error1=%#x error2=%#x\n",
2911 sli_reg_read_status(sli4),
2912 sli_reg_read_err1(sli4),
2913 sli_reg_read_err2(sli4));
2918 if (sli_bmbx_write(sli4)) {
2919 efc_log_crit(sli4, "bmbx write fail phys=%pad reg=%#x\n",
2920 &sli4->bmbx.phys, readl(sli4->reg[0] + SLI4_BMBX_REG));
2927 return sli_cqe_mq(sli4, cqe);
2929 efc_log_crit(sli4, "invalid or wrong type\n");
2934 sli_cmd_config_link(struct sli4 *sli4, void *buf)
2948 sli_cmd_down_link(struct sli4 *sli4, void *buf)
2962 sli_cmd_dump_type4(struct sli4 *sli4, void *buf, u16 wki)
2975 sli_cmd_common_read_transceiver_data(struct sli4 *sli4, void *buf, u32 page_num,
2986 req = sli_config_cmd_init(sli4, buf, psize, dma);
2995 req->port = cpu_to_le32(sli4->port_number);
3001 sli_cmd_read_link_stats(struct sli4 *sli4, void *buf, u8 req_ext_counters,
3025 sli_cmd_read_status(struct sli4 *sli4, void *buf, u8 clear_counters)
3043 sli_cmd_init_link(struct sli4 *sli4, void *buf, u32 speed, u8 reset_alpa)
3068 efc_log_info(sli4, "unsupported FC speed %d\n", speed);
3073 switch (sli4->topology) {
3083 efc_log_info(sli4, "unsupported FC-AL speed %d\n",
3094 efc_log_info(sli4, "unsupported topology %#x\n", sli4->topology);
3111 sli_cmd_init_vfi(struct sli4 *sli4, void *buf, u16 vfi, u16 fcfi, u16 vpi)
3136 sli_cmd_init_vpi(struct sli4 *sli4, void *buf, u16 vpi, u16 vfi)
3150 sli_cmd_post_xri(struct sli4 *sli4, void *buf, u16 xri_base, u16 xri_count)
3168 sli_cmd_release_xri(struct sli4 *sli4, void *buf, u8 num_xri)
3182 sli_cmd_read_config(struct sli4 *sli4, void *buf)
3194 sli_cmd_read_nvparms(struct sli4 *sli4, void *buf)
3206 sli_cmd_write_nvparms(struct sli4 *sli4, void *buf, u8 *wwpn, u8 *wwnn,
3223 sli_cmd_read_rev(struct sli4 *sli4, void *buf, struct efc_dma *vpd)
3248 sli_cmd_read_sparm64(struct sli4 *sli4, void *buf, struct efc_dma *dma, u16 vpi)
3253 efc_log_err(sli4, "special VPI not supported!!!\n");
3258 efc_log_err(sli4, "bad DMA buffer\n");
3280 sli_cmd_read_topology(struct sli4 *sli4, void *buf, struct efc_dma *dma)
3288 efc_log_err(sli4, "loop map buffer too small %zx\n", dma->size);
3310 sli_cmd_reg_fcfi(struct sli4 *sli4, void *buf, u16 index,
3347 sli_cmd_reg_fcfi_mrq(struct sli4 *sli4, void *buf, u8 mode, u16 fcf_index,
3396 sli_cmd_reg_rpi(struct sli4 *sli4, void *buf, u32 rpi, u32 vpi, u32 fc_id,
3436 sli_cmd_reg_vfi(struct sli4 *sli4, void *buf, size_t size,
3458 reg_vfi->e_d_tov = cpu_to_le32(sli4->e_d_tov);
3459 reg_vfi->r_a_tov = cpu_to_le32(sli4->r_a_tov);
3470 sli_cmd_reg_vpi(struct sli4 *sli4, void *buf, u32 fc_id, __be64 sli_wwpn,
3495 sli_cmd_request_features(struct sli4 *sli4, void *buf, u32 features_mask,
3513 sli_cmd_unreg_fcfi(struct sli4 *sli4, void *buf, u16 indicator)
3526 sli_cmd_unreg_rpi(struct sli4 *sli4, void *buf, u16 indicator,
3555 efc_log_info(sli4, "unknown type %#x\n", which);
3566 sli_cmd_unreg_vfi(struct sli4 *sli4, void *buf, u16 index, u32 which)
3594 sli_cmd_unreg_vpi(struct sli4 *sli4, void *buf, u16 indicator, u32 which)
3627 sli_cmd_common_modify_eq_delay(struct sli4 *sli4, void *buf,
3634 req = sli_config_cmd_init(sli4, buf,
3655 sli4_cmd_lowlevel_set_watchdog(struct sli4 *sli4, void *buf,
3660 req = sli_config_cmd_init(sli4, buf,
3672 sli_cmd_common_get_cntl_attributes(struct sli4 *sli4, void *buf,
3677 hdr = sli_config_cmd_init(sli4, buf, SLI4_RQST_CMDSZ(hdr), dma);
3689 sli_cmd_common_get_cntl_addl_attributes(struct sli4 *sli4, void *buf,
3694 hdr = sli_config_cmd_init(sli4, buf, SLI4_RQST_CMDSZ(hdr), dma);
3706 sli_cmd_common_nop(struct sli4 *sli4, void *buf, uint64_t context)
3710 nop = sli_config_cmd_init(sli4, buf, SLI4_CFG_PYLD_LENGTH(cmn_nop),
3724 sli_cmd_common_get_resource_extent_info(struct sli4 *sli4, void *buf, u16 rtype)
3728 ext = sli_config_cmd_init(sli4, buf,
3743 sli_cmd_common_get_sli4_parameters(struct sli4 *sli4, void *buf)
3747 hdr = sli_config_cmd_init(sli4, buf,
3760 sli_cmd_common_get_port_name(struct sli4 *sli4, void *buf)
3764 pname = sli_config_cmd_init(sli4, buf,
3780 sli_cmd_common_write_object(struct sli4 *sli4, void *buf, u16 noc,
3789 wr_obj = sli_config_cmd_init(sli4, buf,
3823 sli_cmd_common_delete_object(struct sli4 *sli4, void *buf, char *obj_name)
3827 req = sli_config_cmd_init(sli4, buf,
3841 sli_cmd_common_read_object(struct sli4 *sli4, void *buf, u32 desired_read_len,
3847 rd_obj = sli_config_cmd_init(sli4, buf,
3880 sli_cmd_dmtf_exec_clp_cmd(struct sli4 *sli4, void *buf, struct efc_dma *cmd,
3885 clp_cmd = sli_config_cmd_init(sli4, buf,
3903 sli_cmd_common_set_dump_location(struct sli4 *sli4, void *buf, bool query,
3910 set_dump_loc = sli_config_cmd_init(sli4, buf,
3946 sli_cmd_common_set_features(struct sli4 *sli4, void *buf, u32 feature,
3951 cmd = sli_config_cmd_init(sli4, buf,
3968 sli_cqe_mq(struct sli4 *sli4, void *buf)
3981 efc_log_info(sli4, "status(st=%#x ext=%#x con=%d cmp=%d ae=%d val=%d)\n",
3994 sli_cqe_async(struct sli4 *sli4, void *buf)
4000 efc_log_err(sli4, "bad parameter sli4=%p buf=%p\n", sli4, buf);
4006 efc_log_info(sli4, "Unsupported by FC link, evt code:%#x\n",
4010 efc_log_info(sli4, "ACQE GRP5\n");
4013 efc_log_info(sli4, "ACQE SLI Port, type=0x%x, data1,2=0x%08x,0x%08x\n",
4019 rc = sli_fc_process_link_attention(sli4, buf);
4022 efc_log_info(sli4, "ACQE unknown=%#x\n", acqe->event_code);
4029 sli_fw_ready(struct sli4 *sli4)
4034 val = sli_reg_read_status(sli4);
4039 sli_wait_for_fw_ready(struct sli4 *sli4, u32 timeout_ms)
4046 if (sli_fw_ready(sli4))
4056 sli_sliport_reset(struct sli4 *sli4)
4063 writel(val, (sli4->reg[0] + SLI4_PORT_CTRL_REG));
4065 rc = sli_wait_for_fw_ready(sli4, SLI4_FW_READY_TIMEOUT_MSEC);
4067 efc_log_crit(sli4, "port failed to become ready after initialization\n");
4073 sli_fw_init(struct sli4 *sli4)
4078 if (!sli_wait_for_fw_ready(sli4, SLI4_FW_READY_TIMEOUT_MSEC)) {
4079 efc_log_crit(sli4, "FW status is NOT ready\n");
4086 return sli_sliport_reset(sli4);
4090 sli_request_features(struct sli4 *sli4, u32 *features, bool query)
4092 struct sli4_cmd_request_features *req_features = sli4->bmbx.virt;
4094 if (sli_cmd_request_features(sli4, sli4->bmbx.virt, *features, query)) {
4095 efc_log_err(sli4, "bad REQUEST_FEATURES write\n");
4099 if (sli_bmbx_command(sli4)) {
4100 efc_log_crit(sli4, "bootstrap mailbox write fail\n");
4105 efc_log_err(sli4, "REQUEST_FEATURES bad status %#x\n",
4115 sli_calc_max_qentries(struct sli4 *sli4)
4121 sli4->qinfo.max_qentries[q] =
4122 sli_convert_mask_to_count(sli4->qinfo.count_method[q],
4123 sli4->qinfo.count_mask[q]);
4131 qentries = sli4->qinfo.max_qentries[q];
4133 efc_log_info(sli4, "[%s]: max_qentries from %d to %d\n",
4135 sli4->qinfo.max_qentries[q], qentries);
4136 sli4->qinfo.max_qentries[q] = qentries;
4141 sli_get_read_config(struct sli4 *sli4)
4143 struct sli4_rsp_read_config *conf = sli4->bmbx.virt;
4147 if (sli_cmd_read_config(sli4, sli4->bmbx.virt)) {
4148 efc_log_err(sli4, "bad READ_CONFIG write\n");
4152 if (sli_bmbx_command(sli4)) {
4153 efc_log_crit(sli4, "bootstrap mailbox fail (READ_CONFIG)\n");
4158 efc_log_err(sli4, "READ_CONFIG bad status %#x\n",
4163 sli4->params.has_extents =
4165 if (sli4->params.has_extents) {
4166 efc_log_err(sli4, "extents not supported\n");
4170 base = sli4->ext[0].base;
4180 sli4->ext[i].number = 1;
4181 sli4->ext[i].n_alloc = 0;
4182 sli4->ext[i].base = &base[i];
4185 sli4->ext[SLI4_RSRC_VFI].base[0] = le16_to_cpu(conf->vfi_base);
4186 sli4->ext[SLI4_RSRC_VFI].size = le16_to_cpu(conf->vfi_count);
4188 sli4->ext[SLI4_RSRC_VPI].base[0] = le16_to_cpu(conf->vpi_base);
4189 sli4->ext[SLI4_RSRC_VPI].size = le16_to_cpu(conf->vpi_count);
4191 sli4->ext[SLI4_RSRC_RPI].base[0] = le16_to_cpu(conf->rpi_base);
4192 sli4->ext[SLI4_RSRC_RPI].size = le16_to_cpu(conf->rpi_count);
4194 sli4->ext[SLI4_RSRC_XRI].base[0] = le16_to_cpu(conf->xri_base);
4195 sli4->ext[SLI4_RSRC_XRI].size = le16_to_cpu(conf->xri_count);
4197 sli4->ext[SLI4_RSRC_FCFI].base[0] = 0;
4198 sli4->ext[SLI4_RSRC_FCFI].size = le16_to_cpu(conf->fcfi_count);
4201 total = sli4->ext[i].number * sli4->ext[i].size;
4202 sli4->ext[i].use_map = bitmap_zalloc(total, GFP_KERNEL);
4203 if (!sli4->ext[i].use_map) {
4204 efc_log_err(sli4, "bitmap memory allocation failed %d\n",
4208 sli4->ext[i].map_size = total;
4211 sli4->topology = (le32_to_cpu(conf->topology_dword) &
4213 switch (sli4->topology) {
4215 efc_log_info(sli4, "FC (unknown)\n");
4218 efc_log_info(sli4, "FC (direct attach)\n");
4221 efc_log_info(sli4, "FC (arbitrated loop)\n");
4224 efc_log_info(sli4, "bad topology %#x\n", sli4->topology);
4227 sli4->e_d_tov = le16_to_cpu(conf->e_d_tov);
4228 sli4->r_a_tov = le16_to_cpu(conf->r_a_tov);
4230 sli4->link_module_type = le16_to_cpu(conf->lmt);
4232 sli4->qinfo.max_qcount[SLI4_QTYPE_EQ] = le16_to_cpu(conf->eq_count);
4233 sli4->qinfo.max_qcount[SLI4_QTYPE_CQ] = le16_to_cpu(conf->cq_count);
4234 sli4->qinfo.max_qcount[SLI4_QTYPE_WQ] = le16_to_cpu(conf->wq_count);
4235 sli4->qinfo.max_qcount[SLI4_QTYPE_RQ] = le16_to_cpu(conf->rq_count);
4242 sli4->qinfo.max_qcount[SLI4_QTYPE_MQ] = SLI4_USER_MQ_COUNT;
4247 sli_get_sli4_parameters(struct sli4 *sli4)
4258 if (sli_cmd_common_get_sli4_parameters(sli4, sli4->bmbx.virt))
4262 (((u8 *)sli4->bmbx.virt) +
4265 if (sli_bmbx_command(sli4)) {
4266 efc_log_crit(sli4, "bootstrap mailbox write fail\n");
4271 efc_log_err(sli4, "COMMON_GET_SLI4_PARAMETERS bad status %#x",
4273 efc_log_err(sli4, "additional status %#x\n",
4285 sli4->params.auto_reg = (dw_loopback & SLI4_PARAM_AREG);
4286 sli4->params.auto_xfer_rdy = (dw_loopback & SLI4_PARAM_AGXF);
4287 sli4->params.hdr_template_req = (dw_loopback & SLI4_PARAM_HDRR);
4288 sli4->params.t10_dif_inline_capable = (dw_loopback & SLI4_PARAM_TIMM);
4289 sli4->params.t10_dif_separate_capable = (dw_loopback & SLI4_PARAM_TSMM);
4291 sli4->params.mq_create_version = GET_Q_CREATE_VERSION(dw_mq_pg_cnt);
4292 sli4->params.cq_create_version = GET_Q_CREATE_VERSION(dw_cq_pg_cnt);
4294 sli4->rq_min_buf_size = le16_to_cpu(parms->min_rq_buffer_size);
4295 sli4->rq_max_buf_size = le32_to_cpu(parms->max_rq_buffer_size);
4297 sli4->qinfo.qpage_count[SLI4_QTYPE_EQ] =
4299 sli4->qinfo.qpage_count[SLI4_QTYPE_CQ] =
4301 sli4->qinfo.qpage_count[SLI4_QTYPE_MQ] =
4303 sli4->qinfo.qpage_count[SLI4_QTYPE_WQ] =
4305 sli4->qinfo.qpage_count[SLI4_QTYPE_RQ] =
4310 sli4->qinfo.count_mask[SLI4_QTYPE_EQ] =
4312 sli4->qinfo.count_method[SLI4_QTYPE_EQ] =
4315 sli4->qinfo.count_mask[SLI4_QTYPE_CQ] =
4317 sli4->qinfo.count_method[SLI4_QTYPE_CQ] =
4320 sli4->qinfo.count_mask[SLI4_QTYPE_MQ] =
4322 sli4->qinfo.count_method[SLI4_QTYPE_MQ] =
4325 sli4->qinfo.count_mask[SLI4_QTYPE_WQ] =
4327 sli4->qinfo.count_method[SLI4_QTYPE_WQ] =
4330 sli4->qinfo.count_mask[SLI4_QTYPE_RQ] =
4332 sli4->qinfo.count_method[SLI4_QTYPE_RQ] =
4336 sli_calc_max_qentries(sli4);
4341 sli4->max_sgl_pages = (dw_sgl_pg_cnt & SLI4_PARAM_SGL_PAGE_CNT_MASK);
4344 sli4->sgl_page_sizes = (dw_sgl_pg_cnt &
4347 sli4->sge_supported_length = le32_to_cpu(parms->sge_supported_length);
4348 sli4->params.sgl_pre_reg_required = (dw_loopback & SLI4_PARAM_SGLR);
4350 sli4->params.sgl_pre_registered = true;
4352 sli4->params.perf_hint = dw_loopback & SLI4_PARAM_PHON;
4353 sli4->params.perf_wq_id_association = (dw_loopback & SLI4_PARAM_PHWQ);
4355 sli4->rq_batch = (le16_to_cpu(parms->dw15w1_rq_db_window) &
4361 sli4->wqe_size = SLI4_WQE_EXT_BYTES;
4363 sli4->wqe_size = SLI4_WQE_BYTES;
4369 sli_get_ctrl_attributes(struct sli4 *sli4)
4381 memset(sli4->vpd_data.virt, 0, sli4->vpd_data.size);
4382 if (sli_cmd_common_get_cntl_attributes(sli4, sli4->bmbx.virt,
4383 &sli4->vpd_data)) {
4384 efc_log_err(sli4, "bad COMMON_GET_CNTL_ATTRIBUTES write\n");
4388 attr = sli4->vpd_data.virt;
4390 if (sli_bmbx_command(sli4)) {
4391 efc_log_crit(sli4, "bootstrap mailbox write fail\n");
4396 efc_log_err(sli4, "COMMON_GET_CNTL_ATTRIBUTES bad status %#x",
4398 efc_log_err(sli4, "additional status %#x\n",
4403 sli4->port_number = attr->port_num_type_flags & SLI4_CNTL_ATTR_PORTNUM;
4405 memcpy(sli4->bios_version_string, attr->bios_version_str,
4406 sizeof(sli4->bios_version_string));
4411 data.virt = dma_alloc_coherent(&sli4->pci->dev, data.size,
4415 efc_log_err(sli4, "Failed to allocate memory for GET_CNTL_ADDL_ATTR\n");
4419 if (sli_cmd_common_get_cntl_addl_attributes(sli4, sli4->bmbx.virt,
4421 efc_log_err(sli4, "bad GET_CNTL_ADDL_ATTR write\n");
4422 dma_free_coherent(&sli4->pci->dev, data.size,
4427 if (sli_bmbx_command(sli4)) {
4428 efc_log_crit(sli4, "mailbox fail (GET_CNTL_ADDL_ATTR)\n");
4429 dma_free_coherent(&sli4->pci->dev, data.size,
4436 efc_log_err(sli4, "GET_CNTL_ADDL_ATTR bad status %#x\n",
4438 dma_free_coherent(&sli4->pci->dev, data.size,
4443 memcpy(sli4->ipl_name, add_attr->ipl_file_name, sizeof(sli4->ipl_name));
4445 efc_log_info(sli4, "IPL:%s\n", (char *)sli4->ipl_name);
4447 dma_free_coherent(&sli4->pci->dev, data.size, data.virt,
4454 sli_get_fw_rev(struct sli4 *sli4)
4456 struct sli4_cmd_read_rev *read_rev = sli4->bmbx.virt;
4458 if (sli_cmd_read_rev(sli4, sli4->bmbx.virt, &sli4->vpd_data))
4461 if (sli_bmbx_command(sli4)) {
4462 efc_log_crit(sli4, "bootstrap mailbox write fail (READ_REV)\n");
4467 efc_log_err(sli4, "READ_REV bad status %#x\n",
4472 sli4->fw_rev[0] = le32_to_cpu(read_rev->first_fw_id);
4473 memcpy(sli4->fw_name[0], read_rev->first_fw_name,
4474 sizeof(sli4->fw_name[0]));
4476 sli4->fw_rev[1] = le32_to_cpu(read_rev->second_fw_id);
4477 memcpy(sli4->fw_name[1], read_rev->second_fw_name,
4478 sizeof(sli4->fw_name[1]));
4480 sli4->hw_rev[0] = le32_to_cpu(read_rev->first_hw_rev);
4481 sli4->hw_rev[1] = le32_to_cpu(read_rev->second_hw_rev);
4482 sli4->hw_rev[2] = le32_to_cpu(read_rev->third_hw_rev);
4484 efc_log_info(sli4, "FW1:%s (%08x) / FW2:%s (%08x)\n",
4488 efc_log_info(sli4, "HW1: %08x / HW2: %08x\n",
4495 efc_log_info(sli4, "VPD length: avail=%d return=%d actual=%d\n",
4501 sli4->vpd_length = le32_to_cpu(read_rev->returned_vpd_length);
4506 sli_get_config(struct sli4 *sli4)
4514 if (sli_get_read_config(sli4))
4517 if (sli_get_sli4_parameters(sli4))
4520 if (sli_get_ctrl_attributes(sli4))
4523 if (sli_cmd_common_get_port_name(sli4, sli4->bmbx.virt))
4527 (((u8 *)sli4->bmbx.virt) +
4530 if (sli_bmbx_command(sli4)) {
4531 efc_log_crit(sli4, "bootstrap mailbox fail (GET_PORT_NAME)\n");
4535 sli4->port_name[0] = port_name->port_name[sli4->port_number];
4536 sli4->port_name[1] = '\0';
4538 if (sli_get_fw_rev(sli4))
4541 if (sli_cmd_read_nvparms(sli4, sli4->bmbx.virt)) {
4542 efc_log_err(sli4, "bad READ_NVPARMS write\n");
4546 if (sli_bmbx_command(sli4)) {
4547 efc_log_crit(sli4, "bootstrap mailbox fail (READ_NVPARMS)\n");
4551 read_nvparms = sli4->bmbx.virt;
4553 efc_log_err(sli4, "READ_NVPARMS bad status %#x\n",
4558 memcpy(sli4->wwpn, read_nvparms->wwpn, sizeof(sli4->wwpn));
4559 memcpy(sli4->wwnn, read_nvparms->wwnn, sizeof(sli4->wwnn));
4561 efc_log_info(sli4, "WWPN %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
4562 sli4->wwpn[0], sli4->wwpn[1], sli4->wwpn[2], sli4->wwpn[3],
4563 sli4->wwpn[4], sli4->wwpn[5], sli4->wwpn[6], sli4->wwpn[7]);
4564 efc_log_info(sli4, "WWNN %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
4565 sli4->wwnn[0], sli4->wwnn[1], sli4->wwnn[2], sli4->wwnn[3],
4566 sli4->wwnn[4], sli4->wwnn[5], sli4->wwnn[6], sli4->wwnn[7]);
4572 sli_setup(struct sli4 *sli4, void *os, struct pci_dev *pdev,
4583 memset(sli4, 0, sizeof(struct sli4));
4585 sli4->os = os;
4586 sli4->pci = pdev;
4589 sli4->reg[i] = reg[i];
4598 efc_log_err(sli4, "SLI_INTF is not valid\n");
4604 efc_log_err(sli4, "Unsupported SLI revision (intf=%#x)\n", intf);
4608 sli4->sli_family = intf & SLI4_INTF_FAMILY_MASK;
4610 sli4->if_type = intf & SLI4_INTF_IF_TYPE_MASK;
4611 efc_log_info(sli4, "status=%#x error1=%#x error2=%#x\n",
4612 sli_reg_read_status(sli4),
4613 sli_reg_read_err1(sli4),
4614 sli_reg_read_err2(sli4));
4623 family = sli4->sli_family;
4632 sli4->asic_type = family;
4633 sli4->asic_rev = rev_id;
4638 if (!sli4->asic_type) {
4639 efc_log_err(sli4, "no matching asic family/rev found: %02x/%02x\n",
4650 sli4->bmbx.size = SLI4_BMBX_SIZE + sizeof(struct sli4_mcqe);
4651 sli4->bmbx.virt = dma_alloc_coherent(&pdev->dev, sli4->bmbx.size,
4652 &sli4->bmbx.phys, GFP_KERNEL);
4653 if (!sli4->bmbx.virt) {
4654 memset(&sli4->bmbx, 0, sizeof(struct efc_dma));
4655 efc_log_err(sli4, "bootstrap mailbox allocation failed\n");
4659 if (sli4->bmbx.phys & SLI4_BMBX_MASK_LO) {
4660 efc_log_err(sli4, "bad alignment for bootstrap mailbox\n");
4664 efc_log_info(sli4, "bmbx v=%p p=0x%x %08x s=%zd\n", sli4->bmbx.virt,
4665 upper_32_bits(sli4->bmbx.phys),
4666 lower_32_bits(sli4->bmbx.phys), sli4->bmbx.size);
4669 sli4->vpd_data.size = 4096;
4670 sli4->vpd_data.virt = dma_alloc_coherent(&pdev->dev,
4671 sli4->vpd_data.size,
4672 &sli4->vpd_data.phys,
4674 if (!sli4->vpd_data.virt) {
4675 memset(&sli4->vpd_data, 0, sizeof(struct efc_dma));
4677 efc_log_info(sli4, "VPD buffer allocation failed\n");
4680 if (!sli_fw_init(sli4)) {
4681 efc_log_err(sli4, "FW initialization failed\n");
4689 sli4->features = (SLI4_REQFEAT_IAAB | SLI4_REQFEAT_NPIV |
4697 if (sli4->params.perf_hint)
4698 sli4->features |= SLI4_REQFEAT_PERFH;
4700 if (sli_request_features(sli4, &sli4->features, true))
4703 if (sli_get_config(sli4))
4710 sli_init(struct sli4 *sli4)
4712 if (sli4->params.has_extents) {
4713 efc_log_info(sli4, "extend allocation not supported\n");
4717 sli4->features &= (~SLI4_REQFEAT_HLM);
4718 sli4->features &= (~SLI4_REQFEAT_RXSEQ);
4719 sli4->features &= (~SLI4_REQFEAT_RXRI);
4721 if (sli_request_features(sli4, &sli4->features, false))
4728 sli_reset(struct sli4 *sli4)
4732 if (!sli_fw_init(sli4)) {
4733 efc_log_crit(sli4, "FW initialization failed\n");
4737 kfree(sli4->ext[0].base);
4738 sli4->ext[0].base = NULL;
4741 bitmap_free(sli4->ext[i].use_map);
4742 sli4->ext[i].use_map = NULL;
4743 sli4->ext[i].base = NULL;
4746 return sli_get_config(sli4);
4750 sli_fw_reset(struct sli4 *sli4)
4755 if (!sli_wait_for_fw_ready(sli4, SLI4_FW_READY_TIMEOUT_MSEC)) {
4756 efc_log_crit(sli4, "FW status is NOT ready\n");
4761 writel(SLI4_PHYDEV_CTRL_FRST, (sli4->reg[0] + SLI4_PHYDEV_CTRL_REG));
4764 if (!sli_wait_for_fw_ready(sli4, SLI4_FW_READY_TIMEOUT_MSEC)) {
4765 efc_log_crit(sli4, "Failed to be ready after firmware reset\n");
4772 sli_teardown(struct sli4 *sli4)
4776 kfree(sli4->ext[0].base);
4777 sli4->ext[0].base = NULL;
4780 sli4->ext[i].base = NULL;
4782 bitmap_free(sli4->ext[i].use_map);
4783 sli4->ext[i].use_map = NULL;
4786 if (!sli_sliport_reset(sli4))
4787 efc_log_err(sli4, "FW deinitialization failed\n");
4789 dma_free_coherent(&sli4->pci->dev, sli4->vpd_data.size,
4790 sli4->vpd_data.virt, sli4->vpd_data.phys);
4791 memset(&sli4->vpd_data, 0, sizeof(struct efc_dma));
4793 dma_free_coherent(&sli4->pci->dev, sli4->bmbx.size,
4794 sli4->bmbx.virt, sli4->bmbx.phys);
4795 memset(&sli4->bmbx, 0, sizeof(struct efc_dma));
4799 sli_callback(struct sli4 *sli4, enum sli4_callback which,
4803 efc_log_err(sli4, "bad parameter sli4=%p which=%#x func=%p\n",
4804 sli4, which, func);
4810 sli4->link = func;
4811 sli4->link_arg = arg;
4814 efc_log_info(sli4, "unknown callback %#x\n", which);
4822 sli_eq_modify_delay(struct sli4 *sli4, struct sli4_queue *eq,
4825 sli_cmd_common_modify_eq_delay(sli4, sli4->bmbx.virt, eq, num_eq,
4828 if (sli_bmbx_command(sli4)) {
4829 efc_log_crit(sli4, "bootstrap mailbox write fail (MODIFY EQ DELAY)\n");
4832 if (sli_res_sli_config(sli4, sli4->bmbx.virt)) {
4833 efc_log_err(sli4, "bad status MODIFY EQ DELAY\n");
4841 sli_resource_alloc(struct sli4 *sli4, enum sli4_resource rtype,
4859 find_first_zero_bit(sli4->ext[rtype].use_map,
4860 sli4->ext[rtype].map_size);
4861 if (position >= sli4->ext[rtype].map_size) {
4862 efc_log_err(sli4, "out of resource %d (alloc=%d)\n",
4863 rtype, sli4->ext[rtype].n_alloc);
4867 set_bit(position, sli4->ext[rtype].use_map);
4870 size = sli4->ext[rtype].size;
4875 *rid = sli4->ext[rtype].base[ext_idx] + item_idx;
4877 sli4->ext[rtype].n_alloc++;
4887 sli_resource_free(struct sli4 *sli4, enum sli4_resource rtype, u32 rid)
4903 base = sli4->ext[rtype].base;
4904 size = sli4->ext[rtype].size;
4914 for (x = 0; x < sli4->ext[rtype].number; x++) {
4919 clear_bit((x * size) + rid, sli4->ext[rtype].use_map);
4932 sli_resource_reset(struct sli4 *sli4, enum sli4_resource rtype)
4942 for (i = 0; i < sli4->ext[rtype].map_size; i++)
4943 clear_bit(i, sli4->ext[rtype].use_map);
4953 int sli_raise_ue(struct sli4 *sli4, u8 dump)
4959 writel(val, (sli4->reg[0] + SLI4_PORT_CTRL_REG));
4965 writel(val, (sli4->reg[0] + SLI4_PHYDEV_CTRL_REG));
4971 int sli_dump_is_ready(struct sli4 *sli4)
4981 port_val = sli_reg_read_status(sli4);
4982 bmbx_val = readl(sli4->reg[0] + SLI4_BMBX_REG);
4995 bool sli_reset_required(struct sli4 *sli4)
4999 val = sli_reg_read_status(sli4);
5004 sli_cmd_post_sgl_pages(struct sli4 *sli4, void *buf, u16 xri,
5012 post = sli_config_cmd_init(sli4, buf,
5048 sli_cmd_post_hdr_templates(struct sli4 *sli4, void *buf, struct efc_dma *dma,
5067 payload_dma->virt = dma_alloc_coherent(&sli4->pci->dev,
5072 efc_log_err(sli4, "mbox payload memory allocation fail\n");
5075 req = sli_config_cmd_init(sli4, buf, payload_size, payload_dma);
5077 req = sli_config_cmd_init(sli4, buf, payload_size, NULL);
5084 rpi = sli4->ext[SLI4_RSRC_RPI].base[0];
5104 sli_fc_get_rpi_requirements(struct sli4 *sli4, u32 n_rpi)
5109 if (sli4->params.hdr_template_req)