Lines Matching defs:iqp
340 struct csio_iq_params iqp;
345 memset(&iqp, 0, sizeof(struct csio_iq_params));
347 csio_mb_iq_alloc_write_rsp(hw, mbp, &retval, &iqp);
355 csio_q_iqid(hw, iq_idx) = iqp.iqid;
356 csio_q_physiqid(hw, iq_idx) = iqp.physiqid;
361 iq_id = iqp.iqid - hw->wrm.fw_iq_start;
368 CSIO_MAX_IQ, iq_id, iqp.iqid, hw->wrm.fw_iq_start);
382 csio_wr_sge_intr_enable(hw, iqp.physiqid);
388 csio_q_flid(hw, flq_idx) = iqp.fl0id;
421 struct csio_iq_params iqp;
424 memset(&iqp, 0, sizeof(struct csio_iq_params));
438 iqp.iqandst = X_INTERRUPTDESTINATION_PCIE;
440 iqp.iqandst = X_INTERRUPTDESTINATION_IQ;
441 iqp.iqandstindex =
445 iqp.iqandst = X_INTERRUPTDESTINATION_PCIE;
446 iqp.iqandstindex = (uint16_t)vec;
454 iqp.pfn = hw->pfn;
455 iqp.vfn = 0;
456 iqp.iq_start = 1;
457 iqp.viid = 0;
458 iqp.type = FW_IQ_TYPE_FL_INT_CAP;
459 iqp.iqasynch = async;
461 iqp.iqanus = X_UPDATESCHEDULING_COUNTER_OPTTIMER;
463 iqp.iqanus = X_UPDATESCHEDULING_TIMER;
464 iqp.iqanud = X_UPDATEDELIVERY_INTERRUPT;
465 iqp.iqpciech = portid;
466 iqp.iqintcntthresh = (uint8_t)csio_sge_thresh_reg;
470 iqp.iqesize = 0; break;
472 iqp.iqesize = 1; break;
474 iqp.iqesize = 2; break;
476 iqp.iqesize = 3; break;
479 iqp.iqsize = csio_q_size(hw, iq_idx) /
481 iqp.iqaddr = csio_q_pstart(hw, iq_idx);
488 iqp.fl0paden = 1;
489 iqp.fl0packen = flq->un.fl.packen ? 1 : 0;
490 iqp.fl0fbmin = X_FETCHBURSTMIN_64B;
491 iqp.fl0fbmax = ((chip == CHELSIO_T5) ?
493 iqp.fl0size = csio_q_size(hw, flq_idx) / CSIO_QCREDIT_SZ;
494 iqp.fl0addr = csio_q_pstart(hw, flq_idx);
497 csio_mb_iq_alloc_write(hw, mbp, priv, CSIO_MB_DEFAULT_TMO, &iqp, cbfn);
637 struct csio_iq_params iqp;
640 memset(&iqp, 0, sizeof(struct csio_iq_params));
646 iqp.pfn = hw->pfn;
647 iqp.vfn = 0;
648 iqp.iqid = csio_q_iqid(hw, iq_idx);
649 iqp.type = FW_IQ_TYPE_FL_INT_CAP;
653 iqp.fl0id = csio_q_flid(hw, flq_idx);
655 iqp.fl0id = 0xFFFF;
657 iqp.fl1id = 0xFFFF;
659 csio_mb_iq_free(hw, mbp, priv, CSIO_MB_DEFAULT_TMO, &iqp, cbfn);