Lines Matching defs:ctrl

478 	phba->ctrl.csr = addr;
484 phba->ctrl.db = addr;
497 phba->ctrl.pcicfg = addr;
545 struct be_ctrl_info *ctrl = &phba->ctrl;
546 struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
547 struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
550 ctrl->pdev = pdev;
566 mutex_init(&ctrl->mbox_lock);
567 spin_lock_init(&phba->ctrl.mcc_lock);
695 mcc = &phba->ctrl.mcc_obj.cq;
754 struct be_ctrl_info *ctrl;
759 ctrl = &phba->ctrl;
760 isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
761 (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
770 mcc = &phba->ctrl.mcc_obj.cq;
1816 mcc_cq = &phba->ctrl.mcc_obj.cq;
1831 beiscsi_process_mcc_compl(&phba->ctrl, mcc_compl);
3050 ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
3114 ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
3172 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
3225 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
3266 &phba->ctrl, &sgl);
3304 status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
3428 status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
3461 struct be_ctrl_info *ctrl = &phba->ctrl;
3466 q = &phba->ctrl.mcc_obj.q;
3470 &ctrl->ptag_state[tag].tag_state))
3474 &ctrl->ptag_state[tag].tag_state)) {
3475 ptag_mem = &ctrl->ptag_state[tag].tag_mem_state;
3477 dma_free_coherent(&ctrl->pdev->dev,
3491 if (waitqueue_active(&ctrl->mcc_wait[tag])) {
3492 ctrl->mcc_tag_status[tag] = MCC_STATUS_FAILED;
3493 ctrl->mcc_tag_status[tag] |= CQE_VALID_MASK;
3494 wake_up_interruptible(&ctrl->mcc_wait[tag]);
3500 &ctrl->ptag_state[tag].tag_state))
3509 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
3513 q = &phba->ctrl.mcc_obj.cq;
3515 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
3524 struct be_ctrl_info *ctrl = &phba->ctrl;
3527 cq = &phba->ctrl.mcc_obj.cq;
3533 if (beiscsi_cmd_cq_create(ctrl, cq,
3538 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
3544 q = &phba->ctrl.mcc_obj.q;
3557 beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
3634 struct be_ctrl_info *ctrl = &phba->ctrl;
3653 be_cmd_iscsi_remove_template_hdr(ctrl);
3658 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
3668 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
3672 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
3676 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
3682 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
3695 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
3701 beiscsi_cmd_special_wrb(&phba->ctrl, 0);
3709 struct be_ctrl_info *ctrl = &phba->ctrl;
3729 status = beiscsi_check_supported_fw(ctrl, phba);
4091 struct be_ctrl_info *ctrl = &phba->ctrl;
4102 addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
4132 struct be_ctrl_info *ctrl = &phba->ctrl;
4134 u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
4829 nonemb_cmd.va = dma_alloc_coherent(&phba->ctrl.pdev->dev,
4838 tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job,
4844 dma_free_coherent(&phba->ctrl.pdev->dev, nonemb_cmd.size,
4850 phba->ctrl.mcc_wait[tag],
4851 phba->ctrl.mcc_tag_status[tag],
4857 &phba->ctrl.ptag_state[tag].tag_state);
4858 dma_free_coherent(&phba->ctrl.pdev->dev, nonemb_cmd.size,
4862 extd_status = (phba->ctrl.mcc_tag_status[tag] &
4864 status = phba->ctrl.mcc_tag_status[tag] & CQE_STATUS_MASK;
4865 free_mcc_wrb(&phba->ctrl, tag);
4875 dma_free_coherent(&phba->ctrl.pdev->dev, nonemb_cmd.size,
5323 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
5324 phba->ctrl.mcc_tag[i] = i + 1;
5325 phba->ctrl.mcc_tag_status[i + 1] = 0;
5326 phba->ctrl.mcc_tag_available++;
5592 ret = beiscsi_get_fw_config(&phba->ctrl, phba);
5598 beiscsi_get_port_name(&phba->ctrl, phba);
5627 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
5628 phba->ctrl.mcc_tag[i] = i + 1;
5629 phba->ctrl.mcc_tag_status[i + 1] = 0;
5630 phba->ctrl.mcc_tag_available++;
5631 memset(&phba->ctrl.ptag_state[i].tag_mem_state, 0,
5635 phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
5725 phba->ctrl.mbox_mem_alloced.size,
5726 phba->ctrl.mbox_mem_alloced.va,
5727 phba->ctrl.mbox_mem_alloced.dma);
5766 /* ctrl uninit */
5769 phba->ctrl.mbox_mem_alloced.size,
5770 phba->ctrl.mbox_mem_alloced.va,
5771 phba->ctrl.mbox_mem_alloced.dma);