Lines Matching refs:intmask_org

127 	u32 intmask_org);
1737 						u32 intmask_org)
1744 		mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
1748 		acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
1754 		mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK |
1759 		acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
1765 		writel(intmask_org & mask, &reg->host_int_mask);
1766 		acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
1773 		writel(intmask_org | mask, reg->pcief0_int_enable);
1781 		writel(intmask_org & mask, &reg->host_int_mask);
2879 			uint32_t intmask_org;
2881 			intmask_org = arcmsr_disable_outbound_ints(acb);
2884 			arcmsr_enable_outbound_ints(acb, intmask_org);
3358 	uint32_t intmask_org;
3362 	intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
3363 	writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
3404 	uint32_t intmask_org;
3407 	intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
3408 	writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, &reg->host_int_mask);
3430 	uint32_t intmask_org;
3433 	intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
3434 	writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, &reg->host_int_mask);
4529 	uint32_t intmask_org;
4531 	intmask_org = arcmsr_disable_outbound_ints(acb);
4540 	arcmsr_enable_outbound_ints(acb, intmask_org);
4547 	uint32_t intmask_org;
4554 		intmask_org = arcmsr_disable_outbound_ints(acb);
4572 		arcmsr_enable_outbound_ints(acb, intmask_org);
4646 	uint32_t intmask_org;
4666 	intmask_org = arcmsr_disable_outbound_ints(acb);
4676 	arcmsr_enable_outbound_ints(acb, intmask_org);