Lines Matching refs:byte
77 #define outp(port, byte) outb((byte), (port))
125 * Narrow boards only support 12-byte commands, while wide boards
126 * extend to 16-byte commands.
865 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
945 uchar reserved1; /* reserved byte (not used) */
1395 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1426 * bus mode override bits [12:10] have been moved to byte register
1726 * All fields in this structure up to byte 60 are used by the microcode.
1748 uchar scsi_status; /* SCSI status byte. */
1778 * Both structures must be 32 byte aligned.
1877 /* Read byte from a register. */
1881 /* Write byte to a register. */
1882 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
1883 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1897 /* Read byte from LRAM. */
1898 #define AdvReadByteLram(iop_base, addr, byte) \
1901 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
1904 /* Write byte to LRAM. */
1905 #define AdvWriteByteLram(iop_base, addr, byte) \
1907 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
2216 unsigned int xfer_sect; /* # 512-byte blocks */
2428 * Print hexadecimal output in 4 byte groupings 32 bytes
3803 * is "transparently" byte-swapped by outpw() and written
3987 /* Ensure overrun buffer is aligned on an 8 byte boundary. */
4094 * 254 word (508 byte) table indexed by byte code followed
4095 * by the following byte codes:
4104 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
4105 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
4500 * device reports it is capable of in Inquiry byte 7.
4689 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
4807 uchar byte;
4855 * Address : I/O base + offset 0x38h register (byte).
4884 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
4885 if ((byte & RAM_TEST_DONE) == 0
4886 || (byte & 0x0F) != PRE_TEST_VALUE) {
4904 * If Done bit not set or Status not 0, save register byte, set the
4910 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
4911 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
4913 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5017 * device reports it is capable of in Inquiry byte 7.
5170 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5293 uchar byte;
5343 * Address : I/O base + offset 0x38h register (byte).
5372 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5373 if ((byte & RAM_TEST_DONE) == 0
5374 || (byte & 0x0F) != PRE_TEST_VALUE) {
5392 * If Done bit not set or Status not 0, save register byte, set the
5398 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5399 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5401 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5512 * device reports it is capable of in Inquiry byte 7.
5659 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
6068 * is passed the microcode ASC_MC_INTRB_CODE byte value.
6249 uchar byte;
6255 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
6256 return byte;
7501 /* This is a byte value, otherwise it would need to be swapped. */
7641 * Multi-byte fields in the ADV_SCSI_REQ_Q that are used by the
7642 * microcode for DMA addresses or math operations are byte swapped
8283 * Multi-byte fields in the ADV_SCSI_REQ_Q that are used by the microcode
8284 * for DMA addresses or math operations are byte swapped to little-endian
9981 * Assume the 6 byte board serial number that was read from
10134 * Assume the 6 byte board serial number that was read from
10361 * Assume the 6 byte board serial number that was read from