Lines Matching defs:data
786 ushort data[ASC_MC_SAVE_DATA_WSIZE];
800 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
802 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
809 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
810 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
812 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
814 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
818 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
820 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
826 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
827 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
832 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
834 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
836 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
838 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
840 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
842 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
844 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
846 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
848 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
850 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
852 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
854 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
856 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
1873 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
3505 * Display data transfer statistics.
3787 * The source data is assumed to be in little-endian order in memory
3814 * The source data is assumed to be in little-endian order in memory
3833 * The source data is assumed to be in little-endian order in LRAM
4069 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4070 (fw->data[1] << 8) | fw->data[0];
4072 if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4435 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4436 (fw->data[1] << 8) | fw->data[0];
4437 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4935 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4936 (fw->data[1] << 8) | fw->data[0];
4937 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5423 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5424 (fw->data[1] << 8) | fw->data[0];
5425 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
8736 sum += wval; /* Checksum treats all EEPROM data as words. */
11313 struct eisa_scsi_data *data;
11316 data = kzalloc(sizeof(*data), GFP_KERNEL);
11317 if (!data)
11359 data->host[i] = shost;
11371 dev_set_drvdata(dev, data);
11375 kfree(data->host[0]);
11376 kfree(data->host[1]);
11377 kfree(data);
11385 struct eisa_scsi_data *data = dev_get_drvdata(dev);
11389 struct Scsi_Host *shost = data->host[i];
11397 kfree(data);