Lines Matching refs:NCR5380_write
103 * NCR5380_write(register, value) - write to the specific register
433 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
434 NCR5380_write(MODE_REG, MR_BASE);
435 NCR5380_write(TARGET_COMMAND_REG, 0);
436 NCR5380_write(SELECT_ENABLE_REG, 0);
737 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
795 NCR5380_write(MODE_REG, MR_BASE);
796 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
894 NCR5380_write(MODE_REG, MR_BASE);
900 NCR5380_write(SELECT_ENABLE_REG, 0);
910 NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask);
996 NCR5380_write(TARGET_COMMAND_REG, 0);
1002 NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask);
1003 NCR5380_write(MODE_REG, MR_ARBITRATE);
1020 NCR5380_write(MODE_REG, MR_BASE);
1024 NCR5380_write(MODE_REG, MR_BASE);
1038 NCR5380_write(MODE_REG, MR_BASE);
1048 NCR5380_write(INITIATOR_COMMAND_REG,
1068 NCR5380_write(MODE_REG, MR_BASE);
1069 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1080 NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask | (1 << scmd_id(cmd)));
1088 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_BSY |
1090 NCR5380_write(MODE_REG, MR_BASE);
1096 NCR5380_write(SELECT_ENABLE_REG, 0);
1107 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA |
1141 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1149 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1171 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);
1186 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1203 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1272 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));
1295 NCR5380_write(OUTPUT_DATA_REG, *d);
1310 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA);
1312 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |
1315 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |
1318 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |
1323 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ACK);
1345 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);
1347 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1389 NCR5380_write(TARGET_COMMAND_REG,
1391 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_RST);
1393 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1415 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);
1434 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));
1437 NCR5380_write(INITIATOR_COMMAND_REG,
1443 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);
1460 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1516 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(p));
1517 NCR5380_write(MODE_REG, MR_BASE | MR_DMA_MODE | MR_MONITOR_BSY |
1536 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1538 NCR5380_write(START_DMA_INITIATOR_RECEIVE_REG, 0);
1541 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_DATA);
1543 NCR5380_write(START_DMA_SEND_REG, 0);
1726 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(tmp));
1728 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN |
1732 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE |
1821 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1850 NCR5380_write(TARGET_COMMAND_REG, 0);
1855 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1869 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1880 NCR5380_write(TARGET_COMMAND_REG, 0);
1899 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1908 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1925 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
1969 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ATN);
2039 NCR5380_write(MODE_REG, MR_BASE);
2057 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_BSY);
2061 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2064 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2082 NCR5380_write(TARGET_COMMAND_REG, PHASE_SR_TO_TCR(PHASE_MSGIN));
2169 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE | ICR_ASSERT_ACK);
2173 NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE);
2331 NCR5380_write(MODE_REG, MR_BASE);
2332 NCR5380_write(TARGET_COMMAND_REG, 0);
2333 NCR5380_write(SELECT_ENABLE_REG, 0);