Lines Matching defs:status_reg_value
240 static int tw_check_bits(u32 status_reg_value)
242 if ((status_reg_value & TW_STATUS_EXPECTED_BITS) != TW_STATUS_EXPECTED_BITS) {
243 dprintk(KERN_WARNING "3w-xxxx: tw_check_bits(): No expected bits (0x%x).\n", status_reg_value);
246 if ((status_reg_value & TW_STATUS_UNEXPECTED_BITS) != 0) {
247 dprintk(KERN_WARNING "3w-xxxx: tw_check_bits(): Found unexpected bits (0x%x).\n", status_reg_value);
255 static int tw_decode_bits(TW_Device_Extension *tw_dev, u32 status_reg_value, int print_host)
266 if (status_reg_value & TW_STATUS_PCI_PARITY_ERROR) {
271 if (status_reg_value & TW_STATUS_PCI_ABORT) {
277 if (status_reg_value & TW_STATUS_QUEUE_ERROR) {
282 if (status_reg_value & TW_STATUS_SBUF_WRITE_ERROR) {
287 if (status_reg_value & TW_STATUS_MICROCONTROLLER_ERROR) {
301 u32 status_reg_value;
305 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev));
308 if (tw_check_bits(status_reg_value))
309 tw_decode_bits(tw_dev, status_reg_value, 0);
311 while ((status_reg_value & flag) != flag) {
312 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev));
314 if (tw_check_bits(status_reg_value))
315 tw_decode_bits(tw_dev, status_reg_value, 0);
330 u32 status_reg_value;
334 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev));
337 if (tw_check_bits(status_reg_value))
338 tw_decode_bits(tw_dev, status_reg_value, 0);
340 while ((status_reg_value & flag) != 0) {
341 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev));
343 if (tw_check_bits(status_reg_value))
344 tw_decode_bits(tw_dev, status_reg_value, 0);
359 u32 status_reg_value;
364 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev));
366 if (tw_check_bits(status_reg_value)) {
368 tw_decode_bits(tw_dev, status_reg_value, 1);
371 if ((status_reg_value & TW_STATUS_COMMAND_QUEUE_FULL) == 0) {
448 u32 status_reg_value;
450 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev));
452 if (TW_STATUS_ERRORS(status_reg_value) || tw_check_bits(status_reg_value)) {
453 tw_decode_bits(tw_dev, status_reg_value, 0);
463 u32 status_reg_value;
465 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev));
467 while ((status_reg_value & TW_STATUS_RESPONSE_QUEUE_EMPTY) == 0) {
469 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev));
548 u32 status_reg_value;
553 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev));
554 if (tw_check_bits(status_reg_value)) {
556 tw_decode_bits(tw_dev, status_reg_value, 1);
595 if ((status_reg_value & TW_STATUS_COMMAND_QUEUE_FULL) == 0) {
2000 u32 status_reg_value;
2011 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev));
2014 if (!(status_reg_value & TW_STATUS_VALID_INTERRUPT))
2024 if (tw_check_bits(status_reg_value)) {
2026 if (tw_decode_bits(tw_dev, status_reg_value, 1)) {
2033 if (status_reg_value & TW_STATUS_HOST_INTERRUPT) {
2039 if (status_reg_value & TW_STATUS_ATTENTION_INTERRUPT) {
2052 if (status_reg_value & TW_STATUS_COMMAND_INTERRUPT) {
2078 if (status_reg_value & TW_STATUS_RESPONSE_INTERRUPT) {
2080 while ((status_reg_value & TW_STATUS_RESPONSE_QUEUE_EMPTY) == 0) {
2176 status_reg_value = inl(TW_STATUS_REG_ADDR(tw_dev));
2177 if (tw_check_bits(status_reg_value)) {
2179 if (tw_decode_bits(tw_dev, status_reg_value, 1)) {