Lines Matching defs:rtc
18 #include <linux/rtc.h>
119 void (*clear_events)(struct stm32_rtc *rtc, unsigned int flags);
137 static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc)
139 const struct stm32_rtc_registers *regs = &rtc->data->regs;
141 writel_relaxed(RTC_WPR_1ST_KEY, rtc->base + regs->wpr);
142 writel_relaxed(RTC_WPR_2ND_KEY, rtc->base + regs->wpr);
145 static void stm32_rtc_wpr_lock(struct stm32_rtc *rtc)
147 const struct stm32_rtc_registers *regs = &rtc->data->regs;
149 writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs->wpr);
152 static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc)
154 const struct stm32_rtc_registers *regs = &rtc->data->regs;
155 unsigned int isr = readl_relaxed(rtc->base + regs->isr);
159 writel_relaxed(isr, rtc->base + regs->isr);
167 return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr, isr,
175 static void stm32_rtc_exit_init_mode(struct stm32_rtc *rtc)
177 const struct stm32_rtc_registers *regs = &rtc->data->regs;
178 unsigned int isr = readl_relaxed(rtc->base + regs->isr);
181 writel_relaxed(isr, rtc->base + regs->isr);
184 static int stm32_rtc_wait_sync(struct stm32_rtc *rtc)
186 const struct stm32_rtc_registers *regs = &rtc->data->regs;
187 unsigned int isr = readl_relaxed(rtc->base + regs->isr);
190 writel_relaxed(isr, rtc->base + regs->isr);
196 return readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr,
202 static void stm32_rtc_clear_event_flags(struct stm32_rtc *rtc,
205 rtc->data->clear_events(rtc, flags);
210 struct stm32_rtc *rtc = (struct stm32_rtc *)dev_id;
211 const struct stm32_rtc_registers *regs = &rtc->data->regs;
212 const struct stm32_rtc_events *evts = &rtc->data->events;
215 rtc_lock(rtc->rtc_dev);
217 status = readl_relaxed(rtc->base + regs->sr);
218 cr = readl_relaxed(rtc->base + regs->cr);
223 dev_dbg(&rtc->rtc_dev->dev, "Alarm occurred\n");
226 rtc_update_irq(rtc->rtc_dev, 1, RTC_IRQF | RTC_AF);
229 stm32_rtc_clear_event_flags(rtc, evts->alra);
232 rtc_unlock(rtc->rtc_dev);
250 * - on rtc side, 0=invalid,1=Monday...7=Sunday
268 * - on rtc side, 0=invalid,1=Monday...7=Sunday
275 struct stm32_rtc *rtc = dev_get_drvdata(dev);
276 const struct stm32_rtc_registers *regs = &rtc->data->regs;
280 tr = readl_relaxed(rtc->base + regs->tr);
281 dr = readl_relaxed(rtc->base + regs->dr);
301 struct stm32_rtc *rtc = dev_get_drvdata(dev);
302 const struct stm32_rtc_registers *regs = &rtc->data->regs;
319 stm32_rtc_wpr_unlock(rtc);
321 ret = stm32_rtc_enter_init_mode(rtc);
327 writel_relaxed(tr, rtc->base + regs->tr);
328 writel_relaxed(dr, rtc->base + regs->dr);
330 stm32_rtc_exit_init_mode(rtc);
332 ret = stm32_rtc_wait_sync(rtc);
334 stm32_rtc_wpr_lock(rtc);
341 struct stm32_rtc *rtc = dev_get_drvdata(dev);
342 const struct stm32_rtc_registers *regs = &rtc->data->regs;
343 const struct stm32_rtc_events *evts = &rtc->data->events;
347 alrmar = readl_relaxed(rtc->base + regs->alrmar);
348 cr = readl_relaxed(rtc->base + regs->cr);
349 status = readl_relaxed(rtc->base + regs->sr);
409 struct stm32_rtc *rtc = dev_get_drvdata(dev);
410 const struct stm32_rtc_registers *regs = &rtc->data->regs;
411 const struct stm32_rtc_events *evts = &rtc->data->events;
414 cr = readl_relaxed(rtc->base + regs->cr);
416 stm32_rtc_wpr_unlock(rtc);
423 writel_relaxed(cr, rtc->base + regs->cr);
426 stm32_rtc_clear_event_flags(rtc, evts->alra);
428 stm32_rtc_wpr_lock(rtc);
473 struct stm32_rtc *rtc = dev_get_drvdata(dev);
474 const struct stm32_rtc_registers *regs = &rtc->data->regs;
503 stm32_rtc_wpr_unlock(rtc);
506 cr = readl_relaxed(rtc->base + regs->cr);
508 writel_relaxed(cr, rtc->base + regs->cr);
514 ret = readl_relaxed_poll_timeout_atomic(rtc->base + regs->isr,
525 writel_relaxed(alrmar, rtc->base + regs->alrmar);
529 stm32_rtc_wpr_lock(rtc);
542 static void stm32_rtc_clear_events(struct stm32_rtc *rtc,
545 const struct stm32_rtc_registers *regs = &rtc->data->regs;
548 writel_relaxed(readl_relaxed(rtc->base + regs->isr) & ~flags,
549 rtc->base + regs->isr);
596 static void stm32mp1_rtc_clear_events(struct stm32_rtc *rtc,
599 struct stm32_rtc_registers regs = rtc->data->regs;
602 writel_relaxed(flags, rtc->base + regs.scr);
628 { .compatible = "st,stm32-rtc", .data = &stm32_rtc_data },
629 { .compatible = "st,stm32h7-rtc", .data = &stm32h7_rtc_data },
630 { .compatible = "st,stm32mp1-rtc", .data = &stm32mp1_data },
636 struct stm32_rtc *rtc)
638 const struct stm32_rtc_registers *regs = &rtc->data->regs;
643 rate = clk_get_rate(rtc->rtc_ck);
654 if (rtc->data->need_accuracy) {
683 cr = readl_relaxed(rtc->base + regs->cr);
685 prer = readl_relaxed(rtc->base + regs->prer);
697 stm32_rtc_wpr_unlock(rtc);
699 ret = stm32_rtc_enter_init_mode(rtc);
706 writel_relaxed(pred_s, rtc->base + regs->prer);
707 writel_relaxed(pred_a | pred_s, rtc->base + regs->prer);
711 writel_relaxed(cr, rtc->base + regs->cr);
713 stm32_rtc_exit_init_mode(rtc);
715 ret = stm32_rtc_wait_sync(rtc);
717 stm32_rtc_wpr_lock(rtc);
724 struct stm32_rtc *rtc;
728 rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL);
729 if (!rtc)
732 rtc->base = devm_platform_ioremap_resource(pdev, 0);
733 if (IS_ERR(rtc->base))
734 return PTR_ERR(rtc->base);
736 rtc->data = (struct stm32_rtc_data *)
738 regs = &rtc->data->regs;
740 if (rtc->data->need_dbp) {
741 rtc->dbp = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
743 if (IS_ERR(rtc->dbp)) {
745 return PTR_ERR(rtc->dbp);
749 1, &rtc->dbp_reg);
756 2, &rtc->dbp_mask);
763 if (!rtc->data->has_pclk) {
764 rtc->pclk = NULL;
765 rtc->rtc_ck = devm_clk_get(&pdev->dev, NULL);
767 rtc->pclk = devm_clk_get(&pdev->dev, "pclk");
768 if (IS_ERR(rtc->pclk))
769 return dev_err_probe(&pdev->dev, PTR_ERR(rtc->pclk), "no pclk clock");
771 rtc->rtc_ck = devm_clk_get(&pdev->dev, "rtc_ck");
773 if (IS_ERR(rtc->rtc_ck))
774 return dev_err_probe(&pdev->dev, PTR_ERR(rtc->rtc_ck), "no rtc_ck clock");
776 if (rtc->data->has_pclk) {
777 ret = clk_prepare_enable(rtc->pclk);
782 ret = clk_prepare_enable(rtc->rtc_ck);
786 if (rtc->data->need_dbp)
787 regmap_update_bits(rtc->dbp, rtc->dbp_reg,
788 rtc->dbp_mask, rtc->dbp_mask);
798 ret = stm32_rtc_init(pdev, rtc);
802 rtc->irq_alarm = platform_get_irq(pdev, 0);
803 if (rtc->irq_alarm <= 0) {
804 ret = rtc->irq_alarm;
812 ret = dev_pm_set_wake_irq(&pdev->dev, rtc->irq_alarm);
816 platform_set_drvdata(pdev, rtc);
818 rtc->rtc_dev = devm_rtc_device_register(&pdev->dev, pdev->name,
820 if (IS_ERR(rtc->rtc_dev)) {
821 ret = PTR_ERR(rtc->rtc_dev);
822 dev_err(&pdev->dev, "rtc device registration failed, err=%d\n",
828 ret = devm_request_threaded_irq(&pdev->dev, rtc->irq_alarm, NULL,
830 pdev->name, rtc);
833 rtc->irq_alarm);
841 if (!(readl_relaxed(rtc->base + regs->isr) & STM32_RTC_ISR_INITS))
845 u32 ver = readl_relaxed(rtc->base + regs->verr);
855 clk_disable_unprepare(rtc->rtc_ck);
857 if (rtc->data->has_pclk)
858 clk_disable_unprepare(rtc->pclk);
860 if (rtc->data->need_dbp)
861 regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0);
871 struct stm32_rtc *rtc = platform_get_drvdata(pdev);
872 const struct stm32_rtc_registers *regs = &rtc->data->regs;
876 stm32_rtc_wpr_unlock(rtc);
877 cr = readl_relaxed(rtc->base + regs->cr);
879 writel_relaxed(cr, rtc->base + regs->cr);
880 stm32_rtc_wpr_lock(rtc);
882 clk_disable_unprepare(rtc->rtc_ck);
883 if (rtc->data->has_pclk)
884 clk_disable_unprepare(rtc->pclk);
887 if (rtc->data->need_dbp)
888 regmap_update_bits(rtc->dbp, rtc->dbp_reg, rtc->dbp_mask, 0);
896 struct stm32_rtc *rtc = dev_get_drvdata(dev);
898 if (rtc->data->has_pclk)
899 clk_disable_unprepare(rtc->pclk);
906 struct stm32_rtc *rtc = dev_get_drvdata(dev);
909 if (rtc->data->has_pclk) {
910 ret = clk_prepare_enable(rtc->pclk);
915 ret = stm32_rtc_wait_sync(rtc);
917 if (rtc->data->has_pclk)
918 clk_disable_unprepare(rtc->pclk);