Lines Matching refs:rtc_dd

71 static int pm8xxx_rtc_read_nvmem_offset(struct pm8xxx_rtc *rtc_dd)
77 	buf = nvmem_cell_read(rtc_dd->nvmem_cell, &len);
80 		dev_dbg(rtc_dd->dev, "failed to read nvmem offset: %d\n", rc);
85 		dev_dbg(rtc_dd->dev, "unexpected nvmem cell size %zu\n", len);
90 	rtc_dd->offset = get_unaligned_le32(buf);
97 static int pm8xxx_rtc_write_nvmem_offset(struct pm8xxx_rtc *rtc_dd, u32 offset)
104 	rc = nvmem_cell_write(rtc_dd->nvmem_cell, buf, sizeof(buf));
106 		dev_dbg(rtc_dd->dev, "failed to write nvmem offset: %d\n", rc);
113 static int pm8xxx_rtc_read_offset(struct pm8xxx_rtc *rtc_dd)
115 	if (!rtc_dd->nvmem_cell)
118 	return pm8xxx_rtc_read_nvmem_offset(rtc_dd);
121 static int pm8xxx_rtc_read_raw(struct pm8xxx_rtc *rtc_dd, u32 *secs)
123 	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
128 	rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value, sizeof(value));
136 	rc = regmap_read(rtc_dd->regmap, regs->read, &reg);
141 		rc = regmap_bulk_read(rtc_dd->regmap, regs->read, value,
152 static int pm8xxx_rtc_update_offset(struct pm8xxx_rtc *rtc_dd, u32 secs)
158 	if (!rtc_dd->nvmem_cell)
161 	rc = pm8xxx_rtc_read_raw(rtc_dd, &raw_secs);
167 	if (offset == rtc_dd->offset)
170 	rc = pm8xxx_rtc_write_nvmem_offset(rtc_dd, offset);
174 	rtc_dd->offset = offset;
188 static int __pm8xxx_rtc_set_time(struct pm8xxx_rtc *rtc_dd, u32 secs)
190 	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
197 	rc = regmap_update_bits_check(rtc_dd->regmap, regs->alarm_ctrl,
203 	rc = regmap_update_bits(rtc_dd->regmap, regs->ctrl, PM8xxx_RTC_ENABLE, 0);
208 	rc = regmap_write(rtc_dd->regmap, regs->write, 0);
213 	rc = regmap_bulk_write(rtc_dd->regmap, regs->write + 1,
219 	rc = regmap_write(rtc_dd->regmap, regs->write, value[0]);
224 	rc = regmap_update_bits(rtc_dd->regmap, regs->ctrl, PM8xxx_RTC_ENABLE,
230 		rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
241 	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
247 	if (rtc_dd->allow_set_time)
248 		rc = __pm8xxx_rtc_set_time(rtc_dd, secs);
250 		rc = pm8xxx_rtc_update_offset(rtc_dd, secs);
256 			secs - rtc_dd->offset, rtc_dd->offset);
262 	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
266 	rc = pm8xxx_rtc_read_raw(rtc_dd, &secs);
270 	secs += rtc_dd->offset;
274 			secs - rtc_dd->offset, rtc_dd->offset);
280 	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
281 	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
287 	secs -= rtc_dd->offset;
290 	rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
295 	rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
301 		rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
314 	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
315 	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
321 	rc = regmap_bulk_read(rtc_dd->regmap, regs->alarm_rw, value,
327 	secs += rtc_dd->offset;
330 	rc = regmap_read(rtc_dd->regmap, regs->alarm_ctrl, &ctrl_reg);
343 	struct pm8xxx_rtc *rtc_dd = dev_get_drvdata(dev);
344 	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
354 	rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
361 		rc = regmap_bulk_write(rtc_dd->regmap, regs->alarm_rw, value,
380 	struct pm8xxx_rtc *rtc_dd = dev_id;
381 	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
384 	rtc_update_irq(rtc_dd->rtc, 1, RTC_IRQF | RTC_AF);
387 	rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl,
393 	rc = regmap_update_bits(rtc_dd->regmap, regs->alarm_ctrl2,
401 static int pm8xxx_rtc_enable(struct pm8xxx_rtc *rtc_dd)
403 	const struct pm8xxx_rtc_regs *regs = rtc_dd->regs;
405 	return regmap_update_bits(rtc_dd->regmap, regs->ctrl, PM8xxx_RTC_ENABLE,
461 	struct pm8xxx_rtc *rtc_dd;
468 	rtc_dd = devm_kzalloc(&pdev->dev, sizeof(*rtc_dd), GFP_KERNEL);
469 	if (rtc_dd == NULL)
472 	rtc_dd->regmap = dev_get_regmap(pdev->dev.parent, NULL);
473 	if (!rtc_dd->regmap)
476 	rtc_dd->alarm_irq = platform_get_irq(pdev, 0);
477 	if (rtc_dd->alarm_irq < 0)
480 	rtc_dd->allow_set_time = of_property_read_bool(pdev->dev.of_node,
483 	rtc_dd->nvmem_cell = devm_nvmem_cell_get(&pdev->dev, "offset");
484 	if (IS_ERR(rtc_dd->nvmem_cell)) {
485 		rc = PTR_ERR(rtc_dd->nvmem_cell);
488 		rtc_dd->nvmem_cell = NULL;
491 	rtc_dd->regs = match->data;
492 	rtc_dd->dev = &pdev->dev;
494 	if (!rtc_dd->allow_set_time) {
495 		rc = pm8xxx_rtc_read_offset(rtc_dd);
500 	rc = pm8xxx_rtc_enable(rtc_dd);
504 	platform_set_drvdata(pdev, rtc_dd);
508 	rtc_dd->rtc = devm_rtc_allocate_device(&pdev->dev);
509 	if (IS_ERR(rtc_dd->rtc))
510 		return PTR_ERR(rtc_dd->rtc);
512 	rtc_dd->rtc->ops = &pm8xxx_rtc_ops;
513 	rtc_dd->rtc->range_max = U32_MAX;
515 	rc = devm_request_any_context_irq(&pdev->dev, rtc_dd->alarm_irq,
518 					  "pm8xxx_rtc_alarm", rtc_dd);
522 	rc = devm_rtc_register_device(rtc_dd->rtc);
526 	rc = dev_pm_set_wake_irq(&pdev->dev, rtc_dd->alarm_irq);