Lines Matching defs:mt2712_rtc
77 struct mt2712_rtc {
85 static inline u32 mt2712_readl(struct mt2712_rtc *mt2712_rtc, u32 reg)
87 return readl(mt2712_rtc->base + reg);
90 static inline void mt2712_writel(struct mt2712_rtc *mt2712_rtc,
93 writel(val, mt2712_rtc->base + reg);
96 static void mt2712_rtc_write_trigger(struct mt2712_rtc *mt2712_rtc)
100 mt2712_writel(mt2712_rtc, MT2712_WRTGR, 1);
102 if (!(mt2712_readl(mt2712_rtc, MT2712_BBPU)
107 dev_err(&mt2712_rtc->rtc->dev,
115 static void mt2712_rtc_writeif_unlock(struct mt2712_rtc *mt2712_rtc)
117 mt2712_writel(mt2712_rtc, MT2712_PROT, MT2712_PROT_UNLOCK1);
118 mt2712_rtc_write_trigger(mt2712_rtc);
119 mt2712_writel(mt2712_rtc, MT2712_PROT, MT2712_PROT_UNLOCK2);
120 mt2712_rtc_write_trigger(mt2712_rtc);
125 struct mt2712_rtc *mt2712_rtc = data;
129 irqsta = mt2712_readl(mt2712_rtc, MT2712_IRQ_STA);
131 rtc_update_irq(mt2712_rtc->rtc, 1, RTC_IRQF | RTC_AF);
138 static void __mt2712_rtc_read_time(struct mt2712_rtc *mt2712_rtc,
141 tm->tm_sec = mt2712_readl(mt2712_rtc, MT2712_TC_SEC)
143 tm->tm_min = mt2712_readl(mt2712_rtc, MT2712_TC_MIN)
145 tm->tm_hour = mt2712_readl(mt2712_rtc, MT2712_TC_HOU)
147 tm->tm_mday = mt2712_readl(mt2712_rtc, MT2712_TC_DOM)
149 tm->tm_mon = (mt2712_readl(mt2712_rtc, MT2712_TC_MTH) - 1)
151 tm->tm_year = (mt2712_readl(mt2712_rtc, MT2712_TC_YEA) + 100)
154 *sec = mt2712_readl(mt2712_rtc, MT2712_TC_SEC) & MT2712_SEC_MASK;
159 struct mt2712_rtc *mt2712_rtc = dev_get_drvdata(dev);
162 if (mt2712_rtc->powerlost)
166 __mt2712_rtc_read_time(mt2712_rtc, tm, &sec);
174 struct mt2712_rtc *mt2712_rtc = dev_get_drvdata(dev);
176 mt2712_writel(mt2712_rtc, MT2712_TC_SEC, tm->tm_sec & MT2712_SEC_MASK);
177 mt2712_writel(mt2712_rtc, MT2712_TC_MIN, tm->tm_min & MT2712_MIN_MASK);
178 mt2712_writel(mt2712_rtc, MT2712_TC_HOU, tm->tm_hour & MT2712_HOU_MASK);
179 mt2712_writel(mt2712_rtc, MT2712_TC_DOM, tm->tm_mday & MT2712_DOM_MASK);
180 mt2712_writel(mt2712_rtc, MT2712_TC_MTH,
182 mt2712_writel(mt2712_rtc, MT2712_TC_YEA,
185 mt2712_rtc_write_trigger(mt2712_rtc);
187 if (mt2712_rtc->powerlost)
188 mt2712_rtc->powerlost = false;
195 struct mt2712_rtc *mt2712_rtc = dev_get_drvdata(dev);
199 irqen = mt2712_readl(mt2712_rtc, MT2712_IRQ_EN);
202 tm->tm_sec = mt2712_readl(mt2712_rtc, MT2712_AL_SEC) & MT2712_SEC_MASK;
203 tm->tm_min = mt2712_readl(mt2712_rtc, MT2712_AL_MIN) & MT2712_MIN_MASK;
204 tm->tm_hour = mt2712_readl(mt2712_rtc, MT2712_AL_HOU) & MT2712_HOU_MASK;
205 tm->tm_mday = mt2712_readl(mt2712_rtc, MT2712_AL_DOM) & MT2712_DOM_MASK;
206 tm->tm_mon = (mt2712_readl(mt2712_rtc, MT2712_AL_MTH) - 1)
208 tm->tm_year = (mt2712_readl(mt2712_rtc, MT2712_AL_YEA) + 100)
217 struct mt2712_rtc *mt2712_rtc = dev_get_drvdata(dev);
220 irqen = mt2712_readl(mt2712_rtc, MT2712_IRQ_EN);
225 mt2712_writel(mt2712_rtc, MT2712_IRQ_EN, irqen);
226 mt2712_rtc_write_trigger(mt2712_rtc);
233 struct mt2712_rtc *mt2712_rtc = dev_get_drvdata(dev);
236 dev_dbg(&mt2712_rtc->rtc->dev, "set al time: %ptR, alm en: %d\n",
239 mt2712_writel(mt2712_rtc, MT2712_AL_SEC,
240 (mt2712_readl(mt2712_rtc, MT2712_AL_SEC)
242 mt2712_writel(mt2712_rtc, MT2712_AL_MIN,
243 (mt2712_readl(mt2712_rtc, MT2712_AL_MIN)
245 mt2712_writel(mt2712_rtc, MT2712_AL_HOU,
246 (mt2712_readl(mt2712_rtc, MT2712_AL_HOU)
248 mt2712_writel(mt2712_rtc, MT2712_AL_DOM,
249 (mt2712_readl(mt2712_rtc, MT2712_AL_DOM)
251 mt2712_writel(mt2712_rtc, MT2712_AL_MTH,
252 (mt2712_readl(mt2712_rtc, MT2712_AL_MTH)
255 mt2712_writel(mt2712_rtc, MT2712_AL_YEA,
256 (mt2712_readl(mt2712_rtc, MT2712_AL_YEA)
261 mt2712_writel(mt2712_rtc, MT2712_AL_MASK, MT2712_AL_MASK_DOW);
262 mt2712_rtc_write_trigger(mt2712_rtc);
270 static void mt2712_rtc_hw_init(struct mt2712_rtc *mt2712_rtc)
274 mt2712_writel(mt2712_rtc, MT2712_BBPU,
277 mt2712_writel(mt2712_rtc, MT2712_CII_EN, 0);
278 mt2712_writel(mt2712_rtc, MT2712_AL_MASK, 0);
280 mt2712_writel(mt2712_rtc, MT2712_CON0, 0x4848);
281 mt2712_writel(mt2712_rtc, MT2712_CON1, 0x0048);
283 mt2712_rtc_write_trigger(mt2712_rtc);
285 p1 = mt2712_readl(mt2712_rtc, MT2712_POWERKEY1);
286 p2 = mt2712_readl(mt2712_rtc, MT2712_POWERKEY2);
288 mt2712_rtc->powerlost = true;
289 dev_dbg(&mt2712_rtc->rtc->dev,
292 mt2712_rtc->powerlost = false;
296 mt2712_writel(mt2712_rtc, MT2712_POWERKEY1, MT2712_POWERKEY1_KEY);
297 mt2712_writel(mt2712_rtc, MT2712_POWERKEY2, MT2712_POWERKEY2_KEY);
298 mt2712_rtc_write_trigger(mt2712_rtc);
300 mt2712_rtc_writeif_unlock(mt2712_rtc);
313 struct mt2712_rtc *mt2712_rtc;
316 mt2712_rtc = devm_kzalloc(&pdev->dev,
317 sizeof(struct mt2712_rtc), GFP_KERNEL);
318 if (!mt2712_rtc)
321 mt2712_rtc->base = devm_platform_ioremap_resource(pdev, 0);
322 if (IS_ERR(mt2712_rtc->base))
323 return PTR_ERR(mt2712_rtc->base);
326 mt2712_rtc_hw_init(mt2712_rtc);
328 mt2712_rtc->irq = platform_get_irq(pdev, 0);
329 if (mt2712_rtc->irq < 0)
330 return mt2712_rtc->irq;
332 platform_set_drvdata(pdev, mt2712_rtc);
334 mt2712_rtc->rtc = devm_rtc_allocate_device(&pdev->dev);
335 if (IS_ERR(mt2712_rtc->rtc))
336 return PTR_ERR(mt2712_rtc->rtc);
338 ret = devm_request_threaded_irq(&pdev->dev, mt2712_rtc->irq, NULL,
341 dev_name(&mt2712_rtc->rtc->dev),
342 mt2712_rtc);
345 mt2712_rtc->irq, ret);
351 mt2712_rtc->rtc->ops = &mt2712_rtc_ops;
352 mt2712_rtc->rtc->range_min = RTC_TIMESTAMP_BEGIN_2000;
353 mt2712_rtc->rtc->range_max = MT2712_RTC_TIMESTAMP_END_2127;
355 return devm_rtc_register_device(mt2712_rtc->rtc);
362 struct mt2712_rtc *mt2712_rtc = dev_get_drvdata(dev);
365 wake_status = enable_irq_wake(mt2712_rtc->irq);
367 mt2712_rtc->irq_wake_enabled = true;
376 struct mt2712_rtc *mt2712_rtc = dev_get_drvdata(dev);
378 if (device_may_wakeup(dev) && mt2712_rtc->irq_wake_enabled) {
379 wake_status = disable_irq_wake(mt2712_rtc->irq);
381 mt2712_rtc->irq_wake_enabled = false;